ARM Instruction Sets, Summaries of Logic

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Jin-Fu Li

Department of Electrical Engineering

National Central University

Jungli, Taiwan

Chapter 4

Chapter 4

ARM Instruction Sets

ARM Instruction Sets

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Registers, Memory Access, and Data Transfer

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Arithmetic and Logic Instructions

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Branch Instructions

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Assembly Language

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I/O Operations

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Subroutines

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Program Examples

Outline

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ARM Processor

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ARM processor was designed by Advanced RISCMachine (ARM) Limited Company

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ARM processors are major used for low-power and lowcost applications ‹

Mobile phones

Communication modems

Automotive engine management systems

Hand-held digital systems

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This chapter introduces the ARM instruction sets basedon the ARM7 processor ‹

Different versions of ARM processors share the same basicmachine instruction sets

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Registers and Memory Access

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In the ARM architecture ‹

Memory is byte addressable

32-bit addresses

32-bit processor registers

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Two operand lengths are used in moving data betweenthe memory and the processor registers ‹

Bytes (8 bits) and words (32 bits)

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Word addresses must be aligned, i.e., they must bemultiple of 4 ‹

Both little-endian and big-endian memory addressing aresupported

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When a byte is loaded from memory into a processorregister or stored from a register into the memory ‹

It always located in the low-order byte position of the register

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Register Structure

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The use of processor mode bits and interrupt disable bitswill be described in conjunction with input/outputoperations and interrupts in Chapter 5

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There are 15 additional general-purpose registers calledthe banked registers ‹

They are duplicates of some of the R0 to R14 registers

They are used when the processor switches into Supervisor orInterrupt modes of operation

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Saved copies of the Status register are also available in theSupervisor and Interrupt modes

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The banked registers and Status register copies will alsobe discussed in Chapter 5

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ARM Instruction Format

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Each instruction is encoded into a 32-bit word

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Access to memory is provided only by Load and Storeinstructions

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The basic encoding format for the instructions, such asLoad, Store, Move, Arithmetic, and Logic instructions, isshown below

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An instruction specifies a conditional execution code(Condition), the OP code, two or three registers (Rn, Rd,and Rm), and some other information

Condition

OP code

Rn

Rd

Rm

Other info

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Memory Addressing Modes

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Pre-indexed mode ‹

The effective address of the operand is the sum of the contents ofthe base register Rn and an offset value

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Pre-indexed with writeback mode ‹

The effective address of the operand is generated in the same wayas in the Pre-indexed mode, and then the effective address iswritten back into Rn

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Post-indexed mode ‹

The effective address of the operand is the contents of Rn. Theoffset is then added to this address and the result is written backinto Rn

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ARM Indexed Addressing Modes

With immediate offset:

Pre-indexedPre-indexed with writebackPost-indexed

With offset in Rn

Pre-indexedPre-indexed with writebackPost-indexed

Relative (Pre-indexed withImmediate offset)

Name

Assembler syntax

Addressing function

[Rn, #offset][Rn, #offset]![Rn], #offest[Rn, +Rm, shift][Rn, +Rm, shift]![Rn], +Rm, shiftLocation

EA=[Rn]+offsetEA=[Rn]+offset; Rn

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[Rn]+offset

EA=[Rn]; Rn

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[Rn]+offset

EA=[Rn]+[Rm] shiftedEA=[Rn]+[Rm] shifted;Rn

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[Rn]+[Rm] shifted

EA=[Rn];Rn

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[Rn]+[Rm] shifted

EA=Location=[PC]+offset

shift=direction #integer, where direction is LSL for left shift or LSR for right shift, and integeris a 5-bit unsigned number specifying the shift format+ Rm=the offset magnitude in register Rm can be added to or subtracted from the contentsof based register Rn

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Pre-Indexed Addressing Mode

STR

R3, [R5,R6]

Operand

200=offset

R

Based register

R

Offset register

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Post-Indexed Addressing with Writeback

100=25x

R

Based register

R

Offset register

100=25x

Load instruction:LDR R1, [R2], R10, LSL, #

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Load/Store Multiple Operands

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In ARM processors, there are two instructions for loadingand storing multiple operands ‹

They are called Block transfer instructions

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Any subset of the general purpose registers can be loadedor stored ‹

Only word operands are allowed, and the OP codes used areLDM (Load Multiple) and STM (Store Multiple)

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The memory operands must be in successive wordlocations

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All of the forms of pre- and post-indexing with andwithout writeback are available

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They operate on a Base register Rn specified in theinstruction and offset is always 4 ‹

LDMIA R10!, {R0,R1,R6,R7}

IA: “Increment After” corresponding to post-indexing

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Arithmetic Instructions

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The basic expression for arithmetic instructions is ‹

OPcode Rd, Rn, Rm

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For example, ADD R0, R2, R4 ‹

Performs the operation R

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[R2]+[R4]

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SUB R0, R6, R5 ‹

Performs the operation R

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[R6]-[R5]

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Immediate mode: ADD R0, R3, #17 ‹

Performs the operation R

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[R3]+

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The second operand can be shifted or rotated before beingused in the operation ‹

For example, ADD R0, R1, R5, LSL #4 operates as follows: thesecond operand stored in R5 is shifted left 4-bit positions(equivalent to [R5]x16), and its is then added to the contents ofR1; the sum is placed in R

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Branch Instructions

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Conditional branch instructions contain a signed 24-bitoffset that is added to the updated contents of theProgram Counter to generate the branch target address

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The format for the branch instructions is shown as below ‹

Offset is a signed 24-bit number. It is shifted left two-bit positions(all branch targets are aligned word addresses), signed extendedto 32 bits, and added to the updated PC to generate the branchtarget address

The updated points to the instruction that is two words (8 bytes)forward from the branch instruction

Condition

OP code

offset

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ARM Branch Instructions

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The BEQ instruction (Branch if Equal to 0) causes abranch if the Z flag is set to 1

BEQ LOCATION

Branch target instruction

Updated [PC]=

LOCATION=

Offset=