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ARMv7 Quick Reference
Arithmetic Instructions ADC{S} rx, ry, op2 rx = ry + op2 + C ADD{S} rx, ry, op2 rx = ry + op ADDW rx, ry, #i 12 rx = ry + i∅^ T ADR rx, ±rel 12 rx = PC ± rel CMN rx, op2 rx + op CMP rx, op2 rx^ −^ op QADD rx, ry, rz rx = SATS(ry + rz, 32) D QDADD rx, ry, rz rx = SATS(ry + SATS(2×rz, 32), 32) D QDSUB rx, ry, rz rx = SATS(ry − SATS(2×rz, 32), 32) D QSUB rx, ry, rz rx = SATS(ry^ −^ rz, 32)^ D RSB{S} rx, ry, op2 rx = op2^ −^ ry RSC{S} rx, ry, op2 rx = op2 − (ry + C) A SBC{S} rx, ry, op2 rx = ry − (op2 + C) SDIV rx, ry, rz rx = ry ¯÷^ rz^7 SSAT rx, #j 5 , ry{slr} rx = SATS(ry^ ^ ¯^ sh, j)±^6 SSAT16 rx, #j 4 , ry rx = SATS(ry± H1, j)±:SATS(ry± H0, j)±^ 6,D SUB{S} rx, ry, op2 rx = ry − op SUBW rx, ry, #i 12 rx = ry^ −^ i∅^ T UDIV rx, ry, rz rx = ry^ ÷^ rz^7 USAD8 rx, ry, rz rx =
n=0(ABS(ry ∅ Bn)−rz ∅ Bn)^ 6,D USADA8 rx, ry, rz, rw rx = rw +
n=0(ABS(ry∅ Bn)−rz∅ Bn)^ 6,D USAT rx, #j 5 , ry{slr} rx = SATU(ry ¯ sh, j)±^6 USAT16 rx, #i 4 , ry rx = SATU(ry± H1, i)±:SATU(ry± H0, i)±^ 6,D
Operand 2 #i 32 i 8 ≫ i 4 :0 (^) A #i 32 024 :i 8 , 0 8 :i 808 :i 8 , i 8 :0 8 i 8 :0 8 or i 8 :i 8 i 8 :i 8 T #i 32 1:i 7 {1..24} T rz rz rz, LSL #n rz {1..31} rz, LSR #n rz {1..32} rz, ASR #n rz {¯ 1..32} rz, ROR #n rz ≫ {1..31} rz, RRX C:rz31:1; C = rz 0 rz, LSL rw rz rw (^) A rz, LSR rw rz rw A rz, ASR rw rz ¯ rw A rz, ROR rw rz ≫ rw (^) A
Bitwise and Move Instructions AND{S} rx, ry, op2 rx = ry & op ASR{S} rx, ry, #j 5 rx = ry^ ¯^ j ASR{S} rx, ry, Rs rx = ry^ ¯^ Rs BFC rx, #p, #n rxp+n−1:p = 0n 6t BFI rx, ry, #p, #n rxp+n−1:p = ryn−1:0 6t BIC{S} rx, ry, op2 rx = ry &^ ∼op CLZ rx, ry rx = CountLeadingZeros(ry) EOR{S} rx, ry, op2 rx = ry^ ⊕^ op LSL{S} rx, ry, #i 5 rx = ry i LSL{S} rx, ry, Rs rx = ry Rs LSR{S} rx, ry, #j 5 rx = ry^ ^ j LSR{S} rx, ry, Rs rx = ry^ ^ Rs MOV{S} rx, op2 rx = op MOVT rx, #i 16 rx31:16 = i 6t MOVW rx, #i 16 rx = i∅ MVN{S} rx, op2 rx =^ ∼op ORN{S} rx, ry, op2 rx = ry | ∼op2 T ORR{S} rx, ry, op2 rx = ry | op RBIT rx, ry rx = ReverseBits(ry) 6t REV rx, ry rx = ryB0:ryB1:ryB2:ryB3 6 REV16 rx, ry rx = ryB2:ryB3:ryB0:ryB1 6 REVSH rx, ry rx = ry± B0:ryB1 6 ROR{S} rx, ry, #i 5 rx = ry ≫ i ROR{S} rx, ry, Rs rx = ry^ ≫^ Rs RRX{S} rx, ry rx = C:ry31:1; C = ry 0 SBFX rx, ry, #p, #n rx = ry± p+n−1:p 6t TEQ rx, op2 rx ⊕ op TST rx, op2 rx & op UBFX rx, ry, #p, #n rx = ry∅ p+n−1:p 6t
Branch and Jump Instructions B rel 26 PC = PC + rel± 25:2:01:0 A B rel 25 PC = PC + rel± 24:1:0 T Bcc rel 21 if(cc) PC = PC + rel± 20:1:0 I BKPT #i 16 BreakPoint(i)^ I BL rel 26 LR=PC31:1:0; PC+=rel± 25:2:01:0 A BL rel 25 LR=PC31:1:1; PC+=rel± 24:1:0 T BLX rel 26 LR=PC31:1:0; Set=1; PC+=rel± 25:1:0 A BLX rel 25 LR=PC31:1:1; Set=0; PC+=rel± 24:2:01:0 T BLX rx LR=PC31:1:0; Set=rx 0 ; PC=rx31:1:0^ A BX rx Set = rx 0 ; PC = rx31:1:0 A TBB [rx, ry] PC = PC + 2 × [rx + ry]∅ 8 T TBH [rx, ry, LSL #1] PC = PC + 2 × [rx + 2 × ry]∅ 16 T
Load and Store Instructions LDMDA rx{!}, rlist rlist = [rx− 4 ×cnt+4]; if(!) rx−=4×cnt A LDMDB rx{!}, rlist rlist = [rx^ −^4 ×cnt]; if(!) rx−=4×cnt LDMIA rx{!}, rlist rlist = [rx]; if(!) rx += 4×cnt LDMIB rx{!}, rlist rlist = [rx + 4]; if(!) rx += 4×cnt A LDR{T} rx, [addr] rx = [addr] LDRB{T} rx, [addr] rx = [addr]∅ 8 LDRD rx, ry, [addr] ry:rx = [addr] LDRH{T} rx, [addr] rx = [addr]∅ 16 LDRSB{T} rx, [addr] rx = [addr]± 8 LDRSH{T} rx, [addr] rx = [addr]± 16 POP rlist rlist = [SP]; SP += 4×cnt PUSH rlist SP^ −= 4×cnt; [SP] = rlist STMDA rx{!}, rlist [rx− 4 ×cnt+4] = rlist; if(!) rx−=4×cnt A STMDB rx{!}, rlist [rx − 4 ×cnt] = rlist; if(!) rx−=4×cnt STMIA rx{!}, rlist [rx] = rlist; if(!) rx += 4×cnt STMIB rx{!}, rlist [rx+4] = rlist; if(!) rx += 4×cnt^ A STR{T} rx, [addr] [addr] = rx STRB{T} rx, [addr] [addr] 8 = rxB STRD rx, ry, [addr] [addr] = ry:rx STRH{T} rx, [addr] [addr] 16 = rxH
ARM LDR/STR Addressing Modes non-T [rz{, #±i 8 }]{!} addr = rz ± i; if(!) rz = addr xxR{,B} [rz{, #±i 12 }]{!} addr = rz ± i; if(!) rz = addr any [rz]{, #±i 8 } addr = rz; rz ±= i xxR{,B}{T} [rz], #±i 12 addr = rz; rz ±= i non-T [rz, ±rw]{!} addr = rz ± rw; if(!) rz = addr xxR{,B} [rz, ±rw{AS}]{!} addr = rz ± AS(rw); if(!) rz = addr any [rz], ±rw addr = rz; rz ±= rw xxR{,B}{T} [rz], ±rw{AS} addr = rz; rz ±= AS(rw) LD non-T ±rel 8 addr = PC ± rel LDR{,B} ±rel 12 addr = PC ± rel
Thumb2 LDR/STR Addressing Modes any [rz{, #i 8 }] addr = rz + i xxR{,B,H,SB,SH} [rz, #i 12 ] addr = rz + i xxR{,B,H,SB,SH} [rz, #±i 8 ]{!} addr = rz ± i; if(!) rz = addr xxR{,B,H,SB,SH} [rz], #±i 8 addr = rz; rz ±= i xxR{,B,H,SB,SH} [rz,rw{,LSL #i 2 }] addr = rz + rw i LDR{,B,H,SB,SH} ±rel 12 addr = PC ± rel xxRD [rz{, #±i 10 }]{!} addr=rz±i9:2:01:0; if(!) rz=addr xxRD [rz], #±i 10 addr = rz; rz ±= i± 9:2:01: LDRD ±rel 10 addr = PC ± rel9:2:01:
Multiplication Instructions MLA rx, ry, rz, rw rx = rw + ry × rz MLA{S} rx, ry, rz, rw rx = rw + ry^ ×^ rz^ A MLS rx, ry, rz, rw rx = rw^ −^ ry^ ×^ rz^ 6t MUL rx, ry, rz rx = ry × rz MUL{S} rx, ry, rz rx = ry × rz A SMLAxy rx, ry, rz, rw rx = rw + ry± Hx ׯ^ rz± Hy D SMLaD rx, ry, rz, rw rx = rw + ry± H0 ׯrz± H0 ±^ ry± H1 ׯrz± H1 6,D SMLaDX rx, ry, rz, rw rx = rw + ry± H0 ׯrz± H1 ±^ ry± H1 ׯrz± H0 D SMLaLD rx, ry, rz, rw ry:rx += rz± H0 ׯrw± H0 ± rz± H1 ׯrw± H1 6,D SMLaLDX rx, ry, rz, rw ry:rx += rz± H0 ׯrw± H1 ± rz± H1 ׯrw± H0 D SMLAL rx, ry, rz, rw ry:rx += rz ¯×^ rw SMLAL{S} rx, ry, rz, rw ry:rx += rz ¯×^ rw^ A SMLALxy rx, ry, rz, rw ry:rx += rz± Hx ׯ rw± Hy D SMLAWy rx, ry, rz, rw rx = rw + ry ¯× rz± Hy D SMMLa rx, ry, rz, rw rx = rw^ ±^ (ry ¯×^ rz)63:32 6,D SMMLaR rx, ry, rz, rw rx = rw^ ±^ (ry ¯×rz + 0x80000000)63:32 D SMMUL rx, ry, rz rx = (ry ¯× rz)63:32 6,D SMMULR rx, ry, rz rx = (ry ¯× rz + 0x80000000)63:32 D SMUaD rx, ry, rz rx = ry± H0 ׯ rz± H0 ± ry± H1 ׯ rz± H1 6,D SMUaDX rx, ry, rz rx = ry± H0 ׯ^ rz± H1 ±^ ry± H1 ׯ^ rz± H0 D SMULxy rx, ry, rz rx = ry± Hx ׯ^ rz± Hy D SMULL rx, ry, rz, rw ry:rx = rz ¯× rw SMULL{S} rx, ry, rz, rw ry:rx = rz ¯× rw A SMULWy rx, ry, rz rx = (ry ¯×^ rz± Hy)47:16 D UMAAL rx, ry, rz, rw ry:rx = ry + rx + rz^ ×^ rw^ D UMLAL rx, ry, rz, rw ry:rx += rz × rw UMULL rx, ry, rz, rw ry:rx = rz × rw
Parallel Instructions pADD16 rx, ry, rz for(n=0..1) rxHn = p(ryHn + rzHn)^ 6,D pADD8 rx, ry, rz for(n=0..3) rxBn = p(ryBn + rzBn)^ 6,D pASX rx, ry, rz rx = p(ryH1 + rzH0):p(ryH0 − rzH1) 6,D pSAX rx, ry, rz rx = p(ryH1 − rzH0):p(ryH0 + rzH1) 6,D pSUB16 rx, ry, rz for(n=0..1) rxHn = p(ryHn − rzHn) 6,D pSUB8 rx, ry, rz for(n=0..3) rxBn = p(ryBn −^ rzBn)^ 6,D SEL rx, ry, rz for(n=0..3) rxBn = (GEn? ry : rz)Bn 6,D
Parallel Instruction Prefixes Q Signed operation, Results are saturated S Signed operation, Results are truncated SH Signed operation, Results are right shifted by one U Unsigned operation, Results are truncated UH Unsigned operation, Results are right shifted by one UQ Unsigned operation, Results are saturated
Packing and Unpacking Instructions PKHBT rx, ry, rz{sl} rx = (rz sh)H1:ryH0 6,D PKHTB rx, ry, rz{sr} rx = ryH1:(rz^ ¯^ sh)H0 6,D SXTAB rx, ry, rz{rb} rx = ry + (rz^ ≫^ sh)± B0 6,D SXTAB16 rx, ry, rz{rb} for(n=0..1) rxHn=ryHn+(rz≫sh)± B2n 6,D SXTAH rx, ry, rz{rb} rx = ry + (rz ≫ sh)± H0 6,D SXTB rx, ry{rb} rx = (ry^ ≫^ sh)± B0 6 SXTB16 rx, ry{rb} for(n=0..1) rxHn = (ry^ ≫^ sh)± B2n 6,D SXTH rx, ry{rb} rx = (ry^ ≫^ sh)± H0 6 UXTAB rx, ry, rz{rb} rx = ry + (rz ≫ sh)∅ B0 6,D UXTAB16 rx, ry, rz{rb} for(n=0..1) rxHn=ryHn+(rz≫sh)∅ B2n 6,D UXTAH rx, ry, rz{rb} rx = ry + (rz^ ≫^ sh)∅ H0 6,D UXTB rx, ry{rb} rx = (ry^ ≫^ sh)∅ B0 6 UXTB16 rx, ry{rb} for(n=0..1) rxHn = (ry ≫ sh)∅ B2n 6,D UXTH rx, ry{rb} rx = (ry ≫ sh)∅ H0 6
Exclusive Load and Store Instructions CLREX ClearExclusiveLocal()^ I,6k LDREX rx, [ry] rx = [ry]; SetExclusiveMonitor^ 6k LDREX rx, [ry, #i 10 ] rx = [ry+i∅ 9:2:01:0]; SetExclusiveMonitor T,6k LDREXB rx, [ry] rx = [ry]∅ 8 ; SetExclusiveMonitor 6k LDREXD rx, ry, [rz] ry:rx = [rz]; SetExclusiveMonitor 6k LDREXH rx, [ry] rx = [ry]∅ 16 ; SetExclusiveMonitor^ 6k STREX rx,ry,[rz] if(Pass) [rz] = ry; rx = Pass? 1 : 0^ 6k STREX rx,ry,[rz,#i 10 ] if(Pass) [rz+i∅ 9:2:01:0]=ry; rx=Pass?1:0 T,6k STREXB rx,ry,[rz] if(Pass) [rz] 8 = ryB0; rx = Pass?1:0 6k STREXD rx,ry,rz,[rw] if(Pass) [rw] = rz:ry; rx = Pass?1:0^ 6k STREXH rx,ry,[rz] if(Pass) [rz] 16 = ryH0; rx = Pass?1:0^ 6k
System Instructions CPSI{D,E} {aif}{, #mode} {a}{i}{f} = (E? 1: 0); MODE = mode 6 CPS #mode MODE = mode 6 ERET PC = LR; CPSR = SPSR^7 HVC #i 16 CallHypervisor(i)^7 MRS rx, xPSR rx = {CPSR,SPSR} MRS rx, Rbanked rx = Rbanked 7 MSR xPSR, rx {CPSR,SPSR} = rx MSR Rbanked, rx Rbanked = rx^7 MSR xPSR {cxsf}, i {CPSR,SPSR}f;s;x;c = if;s;x;c A MSR xPSR {cxsf}, rx {CPSR,SPSR}f;s;x;c = rxf;s;x;c RFEdi rx{!} LDMdi rx{!}, {PC, CPSR} SMC #i 4 CallSecureMonitor()^ 6k SRSdi SP{!}, #mode STMdi SP mode{!},^ {LR, SPSR}^6
Special Instructions DBG #i 4 DebugHint(i) 7 DMB option DataMemoryBarrier(option)^ I, DSB option DataSynchronizationBarrier(option)^ I, ISB SY InstructionSynchronizationBarrier(SY) I, NOP 6k PLD{W} [addr] PreloadData(addr) PLI [addr] PreloadInstr(addr)^7 SETEND {BE/LE} EndianState =^ {BE/LE}^ I, SEV SendEvent() 6k SVC #i 24 CallSupervisor() A UDF #i 16 UndefinedException() WFE WaitForEvent()^ 6k WFI WaitForInterrupt() 6k YIELD HintYield() 6k
Keys {S} Optional suffix, if present update flags {t} Conditional for additional instructions (T or E) {T} LDR/STR instruction uses user privileges. a A or S to add or subtract operand. x, y Selects bottom (B) or top (T) half of register(s) cc Condition code (can suffix most ARM instructions) di DA, DB, IA or IB for decrease/increase before/after. i, j Immediate operand, range 0..max / 1..max+ rx, ry, rz, rw General register Rbanked Banked register rlist Comma separated list of registers within { }. op2 Immediate or shifted register xPSR APSR, CPSR or SPSR SAT{S,U}(x,b) Saturated signed/unsigned b bit value B{0,1,2,3} Selected byte (bits 7:0, 15:8, 23:16 or 31:24) H{0,1} Selected half word (bits 15:0 or 31:16) {rb} Optional rotate (ROR 8, ROR 16 or ROR 24) {slr} Optional shift (LSL #{1..31} or ASR #{1..32}) {sl} Optional left shift (LSL #{1..31}) {sr} Optional right shift (ASR #{1..32}) {AS} ARM shift or rotate (LSL/ROR #{1..31}, LSR/ASR #{1..32} or RRX) value±, value∅^ Value is sign/zero extended ׯ ÷¯ ¯ Operation is signed
ARMv7-A & ARMv7-R System
Current Program Status Register (CPSR) M 0x0000001f Processor Operating Mode T 0x00000020 Instruction set (JT: 00=ARM, 01=Thumb) F 0x00000040 FIQ exception masked I 0x00000080 IRQ exception masked A 0x00000100 Asynchronous abort masked 6 E 0x00000200 Big-endian operation 6 IT 0x0600fc00 IT state bits 6t GE{3..0} 0x000f0000 SIMD Greater than or equal to 6 J 0x01000000 Instr set (JT: 10=Jazelle, 11=ThumbEE) 6 Q 0x08000000 Cumulative saturation bit V 0x10000000 Overflow condition flag C 0x20000000 Carry condition flag Z 0x40000000 Zero condition flag N 0x80000000 Negative condition flag
Processor Operating Modes usr 0x10 User fiq 0x11 FIQ irq 0x12 IRQ svc 0x13 Supervisor mon 0x16 Monitor (Secure only) S abt 0x17 Abort hyp 0x1a Hypervisor (Non-secure only) V und 0x1b Undefined sys 0x1f System
Vectors 0x00 Reset 0x04 Undefined instruction 0x08 Supervisor Call / Secure Monitor Call / Hypervisor Call 0x0c Prefetch abort 0x10 Data abort 0x14 Hyp trap 0x18 IRQ interrupt 0x1c FIQ interrupt
Notes for System Registers and Tables 6,6k,6t,7 Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv A Only present on ARM-A B Banked between secure and non-secure usage R Only present on ARM-R S Only present with security extensions (Implies 6k,A) V Only present with virtualization extensions (Implies 7,A)
System Control Register (SCTLR) M 0x00000001 MMU enabled B A 0x00000002 Alignment check enabled B C 0x00000004 Data and unified caches enabled B CP15BEN 0x00000020 CP15 barrier enable 7,B SW 0x00000400 Enable SWP and SWPB instructions 6,B Z 0x00000800 Program flow prediction enabled B I 0x00001000 Instruction cache enabled B V 0x00002000 High exception vectors B RR 0x00004000 Round Robin select (Non-Secure RO) HA 0x00020000 Hardware access flag enable B,S BR 0x00020000 Background region enable 7,R WXN 0x00080000 Write force to XN V DZ 0x00080000 Divide by zero causes undefined instruction 7,R UWXN 0x00100000 Unprivileged write forced to XN for PL1 V FI 0x00200000 Fast Interrupts (Non-Secure RO) 6 VE 0x01000000 Interrupt Vectors Enable 6,B EE 0x02000000 Exception Endianess 6,B NMFI 0x08000000 Non-maskable FIQ support (RO) 6 TRE 0x10000000 TEX remap functionality enabled B,S AFE 0x20000000 Access flag enable B,S TE 0x40000000 Thumb exception enable 6t,B IE 0x80000000 Big-endian byte order in instructions 7,R
Coprocessor Access Control Register (CPACR) CP{0..13} 3 (2×{0..13}) CP{0..13} access (00=denied, 01=privileged mode only, 11=privileged or user mode) TRCDIS 0x10000000 Disable CP14 access to trace registers D32DIS 0x40000000 Disable use of D16-D31 registers ASEDIS 0x80000000 Disable advanced SIMD functionality
CP15 System Control Registers SCTLR c1,0,c0,0 System Control Register ACTLR c1,0,c0,1 Auxiliary Control Register 6,B CPACR c1,0,c0,2 Coprocessor Access Control Register 6 SCR c1,0,c1,0 Secure Configuration (Secure only) S SDER c1,0,c1,1 Secure Debug Enable (Secure only) S NSACR c1,0,c1,2 Non-Secure Access Control (Non-Secure RO) S
CP15 Security Extension Registers (ARM-A Only) VBAR c12,0,c0,0 Vector Base Register B MVBAR c12,0,c0,1 Monitor Vector Base Address (Secure only) ISR c12,0,c1,0 Interrupt Status Register (RO)
Secure Configuration Register (SCR) NS 0x001 System state is non-secure unless in Monitor mode IRQ 0x002 IRQs taken to Monitor mode FIQ 0x004 FIQs taken to Monitor mode EA 0x008 External aborts taken to Monitor mode FW 0x010 CPSR.F writeable in non-secure state AW 0x020 CPSR.A writeable in non-secure state nET 0x040 Disable early termination SCD 0x080 Secure monitor call disable V HCE 0x100 Hyp Call enable V SIF 0x200 Secure instruction fetch V
Non-Secure Access Control Register (NSACR) CP{0..13} 1 {0..13} CP{0..13} can be accessed in non-secure state NSD32DIS 0x00004000 CPACR.D32DIS is fixed 1 in non-secure state NSASEDIS 0x00008000 CPACR.ASEDIS is fixed 1 in non-secure state RFR 0x00080000 Reserve FIQ mode for non-secure NSTRCDIS 0x00100000 Disable non-secure access to CP14 trace regs
CP15 Memory System Fault Registers DFSR c5,0,c0,0 Data Fault Status Register B IFSR c5,0,c0,1 Instruction Fault Status Register 6,B ADFSR c5,0,c1,0 Auxiliary DFSR 7,B AIFSR c5,0,c1,1 Auxiliary IFSR 7,B DFAR c6,0,c0,0 Data Fault Address Register B IFAR c6,0,c0,2 Instruction Fault Address Register 6,B DRBAR c6,0,c1,0 Data Region Base Address Register R IRBAR c6,0,c1,1 Instruction Region Base Address Register R DRSR c6,0,c1,2 Data Region Size and Enable Register R IRSR c6,0,c1,3 Instruction Region Size and Enable Register R DRACR c6,0,c1,4 Data Region Access Control Register R IRACR c6,0,c1,5 Instruction Region Access Control Register R RGNR c6,0,c2,0 MPU Region Number Register R
CP15 Generic Timer Registers CNTFRQ c14,0,c0,0 Counter Frequency Reg (Non-Secure RO) 7 CNTKCTL c14,0,c1,0 Timer PL1 Control Register 7 CNTP TVAL c14,0,c2,0 PL1 Physical TimerValue Register 7,B CNTP CTL c14,0,c2,1 PL1 Physical Timer Control Register 7,B CNTV TVAL c14,0,c3,0 Virtual TimerValue Register 7 CNTV CTL c14,0,c3,1 Virtual TimerControl Register 7 CNTPCT c14,0 Physical Count Register (RO) 7 CNTVCT c14,1 Virtual Count Register (RO) 7 CNTP CVAL c14,2 PL1 Physical Timer CompareValue Register 7,B CNTV CVAL c14,3 Virtual Timer CompareValue Register 7
CP15 ID Registers (Read-Only) MIDR c0,0,c0,0 Main ID Register CTR c0,0,c0,1 Cache Type Register TCMTR c0,0,c0,2 TCM Type Register TLBTR c0,0,c0,3 TLB Type Register A MPUIR c0,0,c0,4 MPU Type Register R MPIDR c0,0,c0,5 Multiprocessor Affinity Register REVIDR c0,0,c0,6 Revision ID ID PFR{0..1} c0,0,c1,{0..1} Processor Feature Registers 6 ID DFR0 c0,0,c1,2 Debug Feature Register 0 6 ID AFR0 c0,0,c1,3 Auxiliary Feature Register 0 6 ID MMFR{0..3} c0,0,c1,{4..7} Memory Model Feature Regs 6 ID ISAR{0..5} c0,0,c2,{0..5} Instruction Set Attribute Regs 6 CCSIDR c0,1,c0,0 Cache Size ID Register 7 CLIDR c0,1,c0,1 Cache Level ID Register 7 AIDR c0,1,c0,7 Auxiliary ID Register 7 CSSELR c0,2,c0,0 Cache Size Selection Register (RW) 7,B
CP15 Cache Maintenance Registers (Write Only) CP15WFI c7,0,c0,4 Wait for interrupt operation ICIALLUIS c7,0,c1,0 Inv all instr caches to PoU Inner Sharable 7 BPIALLIS c7,0,c1,6 Inv all branche predictors Inner Sharable 7 PAR c7,0,c4,0 Physical Address Register (RW) 7,A,B ICIALLU c7,0,c5,0 Invalidate all instruction caches to PoU ICIMVAU c7,0,c5,1 Inv instruction caches by MVA to PoU CP15ISB c7,0,c5,4 Instruction Sync Barrier operation 7 BPIALL c7,0,c5,6 Invalidate all branch predictors BPIMVA c7,0,c5,7 Invalidate MVA from branch predictors DCIMVAC c7,0,c6,1 Inv data cache line my MVA to PoC DCISW c7,0,c6,2 Invalidate data cache line by set/way ATS1CPR c7,0,c8,0 PL1 read translation (Current state) 7,A ATS1CPW c7,0,c8,1 PL1 write translation (Current state) 7,A ATS1CUR c7,0,c8,2 Unpriv read translation (Current state) 7,A ATS1CUW c7,0,c8,3 Unpriv write translation (Current state) 7,A ATS12NSOPR c7,0,c8,4 PL1 read translation (NS state) 7,S ATS12NSOPW c7,0,c8,5 PL1 write translation (NS state) 7,S ATS12NSOUR c7,0,c8,6 Unprivileged read translation (NS state) 7,S ATS12NSOUW c7,0,c8,7 Unprivileged write translation (NS state) 7,S DCCMVAC c7,0,c10,1 Clean data cache line my MVA to PoC DCCSW c7,0,c10,2 Clean data cache line by set/way CP15DSB c7,0,c10,4 Data Synchronization Barrier operation 7 CP15DMB c7,0,c10,5 Data Memory Barrier operation 7 DCCMVAU c7,0,c11,1 Clean data cache line by MVA to PoU DCCIMVAC c7,0,c14,1 Clean and inv data c-line by MVA to PoC DCCISW c7,0,c14,2 Clean and inv data c-line by set/way PAR c7,0 Physical Address Register (RW) 7,A,B
CP15 Memory Protection and Control Registers (ARM-A only) TTBR0 c2,0,c0,0 Translation Table Base 0 B TTBR1 c2,0,c0,1 Translation Table Base 1 6,B TTBCR c2,0,c0,2 Translation Table Base Control 6,B TTBR0 c2,0 Translation Table Base 0 (LPAE only) 7,B TTBR1 c2,1 Translation Table Base 1 (LPAE only) 7,B DACR c3,0,c0,0 Domain Access Control Register B
CP15 TLB Maintenance Operation Regs (Write Only, ARM-A Only) TLBIALLIS c8,0,c3,0 Invalidate entire TLB IS 7 TLBIMVAIS c8,0,c3,1 Invalidate unified TLB by MVA and ASID IS 7 TLBIASIDIS c8,0,c3,2 Invalidate unified TLB by ASID match IS 7 TLBIMVAAIS c8,0,c3,3 Inv unified TLB entry by MVA all ASID IS 7 ITLIALL c8,0,c5,0 Invalidate instruction TLB ITLIMVA c8,0,c5,1 Inv instr TLB entry by MVA all ASID IS ITLIASID c8,0,c5,2 Invalidate instruction TLB by ASID match 6 DTLBIALL c8,0,c6,0 Invalidate data TLB DTLBIMVA c8,0,c6,1 Invalidate data TLB entry by MVA and ASID DTLBIASID c8,0,c6,2 Invalidate data TLB by ASID match 6 TLBIALL c8,0,c7,0 Invalidate unified TLB TLBIMVA c8,0,c7,1 Inv unified TLB entry by MVA and ASID TLBIASID c8,0,c7,2 Invalidate unified TLB by ASID match 6 TLBIMVAA c8,0,c7,3 Inval unified TLB entries by MVA all ASID 6
CP15 Performance Monitor Registers (ARM-R Only) PMCR c9,0,c12,0 PM Control Register PMCNTENSET c9,0,c12,1 PM Count Enable Set Register PMCNTENCLR c9,0,c12,2 PM Count Enable Clear Register PMOVSR c9,0,c12,3 PM Overflow Flag Status Register PMSWINC c9,0,c12,4 PM Software Increment Register PMSELR c9,0,c12,5 PM Event Counter Selection Register PMCEID0 c9,0,c12,6 PM Common Event Identification Register 0 PMCEID1 c9,0,c12,7 PM Common Event Identification Register 1 PMCCNTR c9,0,c13,0 PM Cycle Count Register PMXEVTYPER c9,0,c13,1 PM Event Type Select Register PMXEVCNTR c9,0,c13,2 PM Event Count Register PMUSERENR c9,0,c14,0 PM User Enable Register PMINTENSET c9,0,c14,1 PM Interrupt Enable Set Register PMINTENCLR c9,0,c14,2 PM Interrupt Enable Clear Register
CP15 Memory Mapping Registers (ARM-A Only) PRRR c10,0,c2,0 Primary Region Remap Register 6,B NMRR c10,0,c2,1 Normal Memory Remap Register 6,B AMAIR0 c10,0,c3,0 Aux Memory Attribute Indirection Reg 0 7 AMAIR1 c10,0,c3,1 Aux Memory Attribute Indirection Reg 1 7
CP15 Process, Context, and Thread ID Registers FCSEIDR c13,0,c0,0 FSCE PID Register A,B CONTEXIDR c13,0,c0,1 Context ID Register 6,B TPIDRURW c13,0,c0,2 User Read/Write Thread ID 6,B TPIDRURO c13,0,c0,3 User Read-only Thread ID 6,B TPIDRPRW c13,0,c0,4 PL1 only Thread ID 6,B
CP15 Virtualization Extension Registers (ARM-A Only) VPIDR c0,4,c0,0 Virtualization Processor ID Register VMPIDR c0,4,c0,5 Virtualization Multiproc ID Register HSCTLR c1,4,c0,0 Hyp System Control Register HACTLR c1,4,c0,1 Hyp Auxiliary Control Register HCR c1,4,c1,0 Hyp Configuration Register HDCR c1,4,c1,1 Hyp Debug Configuration Register HCPTR c1,4,c1,2 Hyp Coprocessor Trap Register HSTR c1,4,c1,3 Hyp System Trap Register HACR c1,4,c1,7 Hyp Auxiliary Configuration Register HTCR c2,4,c0,2 Hyp Translation Control Register VTCR c2,4,c1,2 Virtualization Translation Control Reg HTTBR c2,4 Hyp Translation Table Base Reg VTTBR c2,6 Virt Translation Table Base Reg HADFSR c5,4,c1,0 Hyp Auxiliary DFSR HAIFSR c5,4,c1,1 Hyp Auxiliary IFSR HSR c5,4,c2,0 Hyp Syndrome Register HDFAR c6,4,c0,0 Hyp Data Fault Address Register HIFAR c6,4,c0,2 Hyp Instruction Fault Address Register HPFAR c6,4,c0,4 Hyp IPA Fault Address Register ATS1HR c7,4,c8,0 Addr Tran Stage 1 Hyp mode Read (WO) ATS1HW c7,4,c8,1 Addr Tran Stage 1 Hyp mode Write (WO) TLBIALLHIS c8,4,c3,0 Inv entry hyp unif TLB IS (WO) TLBIMVAHIS c8,4,c3,1 Inv hyp unif TLB entry by MVA IS (WO) TLBIALLNSNHIS c8,4,c3,4 Inv non-sec/hyp uni TLB IS (WO) TLBIALLH c8,4,c7,0 Inv hyp unified (WO) TLBIMVAH c8,4,c7,1 Inv hyp unif TLB by MVA (WO) TLBIALLNSNH c8,4,c7,4 Inv non-sec/hyp unif TLB (WO) HMAIR0 c10,4,c2,0 Hyp Mem Attribute Indirection Reg 0 HMAIR1 c10,4,c2,1 Hyp Mem Attribute Indirection Reg 1 HAMAIR0 c10,4,c3,0 Hyp Aux Mem Attr Indirection Reg 0 HAMAIR1 c10,4,c3,1 Hyp Aux Mem Attr Indirection Reg 1 HVBAR c12,4,c0,0 Hyp Vector Base Address Register HTPIDR c13,4,c0,2 Hyp Read/Write Thread ID CNTHCTL c14,4,c1,0 Timer PL2 Control Register CNTHP TVAL c14,4,c2,0 PL2 Physical TimerValue Register CNTHP CTL c14,4,c2,1 PL2 Physical Timer Control Register CNTVOFF c14,4 Virtual Offset Register CNTHP CVAL c14,6 PL2 Physical Timer CompareValue Register
