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x86 / x86-64 Assembly Language
Introductory Reference — Registers, Instructions & Addressing
1. Registers
Registers are small, extremely fast storage locations built directly into the CPU. In x86-64 there are
16 general-purpose registers (GPRs), each 64 bits wide, plus specialised registers for flags and
the instruction pointer.
1.1 General-Purpose Registers Register (64-bit) 32 / 16 / 8-bit aliases Conventional use RAX (^) EAX / AX / AL Accumulator — return values, arithmetic RBX (^) EBX / BX / BL Base — callee-saved, general use RCX (^) ECX / CX / CL Counter — loop counter, 4th argument (Windows) RDX (^) EDX / DX / DL Data — I/O, 3rd argument, high half of mul/div RSI (^) ESI / SI / SIL Source index — 2nd argument (Linux), string ops RDI (^) EDI / DI / DIL Destination index — 1st argument (Linux), string ops RSP (^) ESP / SP / SPL Stack pointer — always points to top of stack RBP (^) EBP / BP / BPL Base pointer — stack frame base (callee-saved) R8–R15 (^) R8D–R15D / R8W–R15W / R8B–R15B Additional GPRs (x86-64 only) 1.2 Special-Purpose Registers Register Purpose RIP (^) Instruction pointer — address of the next instruction to execute. Not directly writable; changed by JMP, CALL, RET. RFLAGS (^) Status flags register — individual bits record the outcome of the last operation (Zero Flag, Carry Flag, Sign Flag, Overflow Flag, etc.). XMM0–XMM15 (^) 128-bit SIMD registers used for floating-point and packed integer operations (SSE/SSE2). 1.3 Key RFLAGS Bits Flag Bit Set when… ZF — Zero (^6) Result of last operation was zero CF — Carry (^0) Unsigned overflow (carry out of MSB) SF — Sign (^7) Result was negative (MSB = 1) OF — Overflow (^11) Signed overflow occurred
Flag Bit Set when… PF — Parity (^2) Least-significant byte has even number of 1 bits
2. Addressing Modes
An addressing mode describes how an instruction locates its operand(s). x86 offers several
modes, which can be combined.
Mode Syntax example Meaning Immediate (^) MOV RAX, 42 Operand is a constant embedded in the instruction Register (^) MOV RAX, RBX Operand lives in a named register Direct / Absolute (^) MOV RAX, [0x4000] Operand is at a fixed memory address Register Indirect (^) MOV RAX, [RBX] Address is the value stored in RBX Base + Displacement (^) MOV RAX, [RBX+8] Address = RBX + constant offset (accessing struct fields) Base + Index (^) MOV RAX, [RBX+RCX] Address = RBX + RCX (two registers added) Base+Index×Scale+Di sp MOV RAX, [RBX+RCX*4+8] Full form: base + (index × 1/2/4/8) + displacement RIP-relative (^) MOV RAX, [RIP+offset] 64-bit mode: address relative to next instruction (used for globals)
Size specifiers. When the operand size cannot be inferred from the registers, use an explicit
specifier: BYTE PTR (8-bit), WORD PTR (16-bit), DWORD PTR (32-bit), QWORD PTR (64-bit). Example:
MOV BYTE PTR [RAX], 0.
3. Core Instructions 3.1 Data Movement Instruction Example Effect MOV dst, src (^) MOV RAX, RBX Copy src into dst (src unchanged) MOVZX dst, src (^) MOVZX EAX, BL Move with zero-extension (fills upper bits with 0) MOVSX dst, src (^) MOVSX RAX, EBX Move with sign-extension (fills upper bits with sign bit) LEA dst, [mem] (^) LEA RAX, [RBX+8] Load Effective Address — stores the computed address, not the value at it XCHG a, b (^) XCHG RAX, RBX Atomically swap two operands PUSH src (^) PUSH RAX Decrement RSP by 8, write src to [RSP] POP dst (^) POP RBX Read [RSP] into dst, increment RSP by 8
4. Calling Conventions (Quick Reference)
When a function is called, arguments are passed and the stack is managed according to a calling
convention. The two most common in x86-64 are:
System V AMD64 (Linux / macOS) Microsoft x64 (Windows) Integer args (order)
RDI, RSI, RDX, RCX, R8, R9 RCX, RDX, R8, R
Float args (^) XMM0–XMM7 XMM0–XMM Return value (^) RAX (int) / XMM0 (float) RAX (int) / XMM0 (float) Callee-saved (^) RBX, RBP, R12–R15 RBX, RBP, RDI, RSI, R12–R Caller-saved (^) RAX, RCX, RDX, RSI, RDI, R8–R11 RAX, RCX, RDX, R8–R Stack alignment (^) 16-byte aligned before CALL 16-byte aligned; 32-byte shadow space
5. Common Idioms & Tips Idiom / Pattern Explanation XOR RAX, RAX (^) Zero a register — faster and shorter than MOV RAX, 0 TEST RAX, RAX (^) Check if RAX is zero without modifying it (sets ZF if zero). Equivalent to CMP RAX, 0 but one byte shorter. LEA RCX, [RAX+RAX2] (^) Compute RAX3 without a MUL instruction — LEA is often used for cheap arithmetic. PUSH RBP / MOV RBP, RSP (^) Standard function prologue: save old base pointer, set new frame. MOV RSP, RBP / POP RBP / RET Standard function epilogue: restore stack and return. SHL RAX, 2 (^) Multiply RAX by 4 (2^2) — shift is faster than IMUL for powers of two. AND RAX, -1 (^) No-op in terms of value but useful to set flags. AND RAX, 0xF masks to lower nibble. CDQE / CDQ (^) Sign-extend EAX into RAX (CDQE) or RAX into RDX:RAX (CDQ) before a signed divide. Notation: dst = destination operand, src = source operand, [ ] = memory dereference, cnt = shift count (immediate or CL register). Intel syntax used throughout (destination first).
