ECE4100/6100: Assignment 4
Due Date: December 4th, 2003
Part 1:
1. Problem 6.5 in the text (H&P).
2. Write an expression for the bisection bandwidth of the following networks.
a. A 8x6x2 torus with W bit wide full duplex channels
b. A 64 processor machine interconnect with an indirect multistage network
(Figure 8.13 b) with W bit wide channels.
c. A N processor system connected by a 64 bit wide bus.
d. A 128 node binary hypercube with single bit channels.
Part 2: Project
Implement the shared memory cache coherence protocol described in Figure 6.11.
1. Define a format for your input address trace
a. include address and reference type, e.g., Read or Write
b. distinguish between a local processor references and a reference snooped
on the bus
2. Simulate the directory protocol for a 64 Kbyte direct mapped cache with 32 byte
lines. Note that you only need to simulate relevant directory entries and not the
data cache.
3. Provide a test case, i.e., a file with a sequence of addresses, that demonstrates
your protocol implementation is correct.
4. Your implementation should be in ANSI standard C or C++. Exceptions should
be discussed with the TA.
5. Attach a README covering the execution of the program
6. Ensue your program is well documented.
7. Email the program and README to the TA by end of day (midnite) December
4th.
If you wish to pursue an alternative project, please send me a brief description and/or see
me. Examples of alternative projects include
1. Visualization of the shared memory protocol for more than one processor (two
students
2. Visualization of Tomasulo’s algorithm.
3. Simulation of a multilevel cache