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AVR-instructions-sheet, Cheat Sheet of Computer Science

Middle East Technical UniversityComputer Science

AVR instructions sheet for to use in exams etc.

Typology: Cheat Sheet

2022/2023

Uploaded on 11/24/2023

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bishop-brown ๐Ÿ‡น๐Ÿ‡ท

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bg1
Instruction Set
4
Complete Instruction Set Summary
Notes: 1. Not all instructions are available in all devices. Refer to the device specific instruction summary.
2. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external
RAM interface. For LD, ST, LDS, STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL, ICALL,
EICALL, RCALL, RET, RETI in devices with 16 bit PC, add three cycles plus two cycles for each wait state. For CALL,
ICALL, EICALL, RCALL, RET, RETI in devices with 22 bit PC, add five cycles plus three cycles for each wait state.
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clock Note
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd โ† Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd โ† Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd+1:Rd โ† Rd+1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd โ† Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd โ† Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd โ† Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd โ† Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd+1:Rd โ† Rd+1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd โ† Rd โ€ข Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd โ† Rd โ€ข K Z,N,V,S 1
OR Rd, Rr Logical OR Rd โ† Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd โ† Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd โ† Rd โŠ• Rr Z,N,V,S 1
COM Rd Oneโ€™s Complement Rd โ† $FF - Rd Z,C,N,V,S 1
NEG Rd Twoโ€™s Complement Rd โ† $00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd โ† Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd โ† Rd โ€ข ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd โ† Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd โ† Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd โ† Rd โ€ข Rd Z,N,V,S 1
CLR Rd Clear Register Rd โ† Rd โŠ• Rd Z,N,V,S 1
SER Rd Set Register Rd โ† $FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 โ† Rd ร— Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 โ† Rd ร— Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 โ† Rd ร— Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 โ† (Rd ร— Rr)<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 โ† (Rd ร— Rr)<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with
Unsigned
R1:R0 โ† (Rd ร— Rr)<<1 (SU) Z,C 2
pf3
pf4
pf5

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4 Instruction Set

Complete Instruction Set Summary

Notes: 1. Not all instructions are available in all devices. Refer to the device specific instruction summary.

  1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. For LD, ST, LDS, STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL, ICALL, EICALL, RCALL, RET, RETI in devices with 16 bit PC, add three cycles plus two cycles for each wait state. For CALL, ICALL, EICALL, RCALL, RET, RETI in devices with 22 bit PC, add five cycles plus three cycles for each wait state.

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clock Note Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd โ† Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd โ† Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd+1:Rd โ† Rd+1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd โ† Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd โ† Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd โ† Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd โ† Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd+1:Rd โ† Rd+1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd โ† Rd โ€ข Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd โ† Rd โ€ข K Z,N,V,S 1 OR Rd, Rr Logical OR Rd โ† Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd โ† Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd โ† Rd โŠ• Rr Z,N,V,S 1 COM Rd Oneโ€™s Complement Rd โ† $FF - Rd Z,C,N,V,S 1 NEG Rd Twoโ€™s Complement Rd โ† $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd โ† Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd โ† Rd โ€ข ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd โ† Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd โ† Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd โ† Rd โ€ข Rd Z,N,V,S 1 CLR Rd Clear Register Rd โ† Rd โŠ• Rd Z,N,V,S 1 SER Rd Set Register Rd โ† $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 โ† Rd ร— Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 โ† Rd ร— Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 โ† Rd ร— Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 โ† (Rd ร— Rr)<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 โ† (Rd ร— Rr)<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned

R1:R0 โ† (Rd ร— Rr)<<1 (SU) Z,C 2

Instruction Set

5

BRGE k Branch if Greater or Equal, Instruction Set Summary (Continued)

  • RJMP k Relative Jump PC โ† PC + k + 1 None Branch Instructions
  • IJMP Indirect Jump to (Z) PC(15:0) โ† Z, PC(21:16) โ† 0 None
  • EIJMP Extended Indirect Jump to (Z) PC(15:0) โ† Z, PC(21:16) โ† EIND None
  • JMP k Jump PC โ† k None
  • RCALL k Relative Call Subroutine PC โ† PC + k + 1 None 3 /
  • ICALL Indirect Call to (Z) PC(15:0) โ† Z, PC(21:16) โ† 0 None 3 /
  • EICALL Extended Indirect Call to (Z) PC(15:0) โ† Z, PC(21:16) โ† EIND None
  • CALL k Call Subroutine PC โ† k None 4 /
  • RET Subroutine Return PC โ† STACK None 4 /
  • RETI Interrupt Return PC โ† STACK I 4 /
  • CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC โ† PC + 2 or 3 None 1 / 2 /
  • CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H
  • CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H
  • CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H
  • SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC โ† PC + 2 or 3 None 1 / 2 /
  • SBRS Rr, b Skip if Bit in Register Set if (Rr(b)=1) PC โ† PC + 2 or 3 None 1 / 2 /
  • SBIC A, b Skip if Bit in I/O Register Cleared if(I/O(A,b)=0) PC โ† PC + 2 or 3 None 1 / 2 /
  • SBIS A, b Skip if Bit in I/O Register Set If(I/O(A,b)=1) PC โ† PC + 2 or 3 None 1 / 2 /
  • BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC โ†PC+k + 1 None 1 /
  • BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC โ†PC+k + 1 None 1 /
  • BREQ k Branch if Equal if (Z = 1) then PC โ† PC + k + 1 None 1 /
  • BRNE k Branch if Not Equal if (Z = 0) then PC โ† PC + k + 1 None 1 /
  • BRCS k Branch if Carry Set if (C = 1) then PC โ† PC + k + 1 None 1 /
  • BRCC k Branch if Carry Cleared if (C = 0) then PC โ† PC + k + 1 None 1 /
  • BRSH k Branch if Same or Higher if (C = 0) then PC โ† PC + k + 1 None 1 /
  • BRLO k Branch if Lower if (C = 1) then PC โ† PC + k + 1 None 1 /
  • BRMI k Branch if Minus if (N = 1) then PC โ† PC + k + 1 None 1 /
  • BRPL k Branch if Plus if (N = 0) then PC โ† PC + k + 1 None 1 /
    • if (N โŠ• V= 0) then PC โ† PC + k + 1 None 1 / Signed
  • BRLT k Branch if Less Than, Signed if (N โŠ• V= 1) then PC โ† PC + k + 1 None 1 /
  • BRHS k Branch if Half Carry Flag Set if (H = 1) then PC โ† PC + k + 1 None 1 /
  • BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC โ† PC + k + 1 None 1 /
  • BRTS k Branch if T Flag Set if (T = 1) then PC โ† PC + k + 1 None 1 /
  • BRTC k Branch if T Flag Cleared if (T = 0) then PC โ† PC + k + 1 None 1 /

Instruction Set

ST -Z, Rr Store Indirect and Pre- Decrement

Z โ† Z - 1, (Z) โ† Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) โ† Rr None 2 LPM Load Program Memory R0 โ† (Z) None 3 LPM Rd, Z Load Program Memory Rd โ† (Z) None 3 LPM Rd, Z+ Load Program Memory and Post- Increment

Rd โ† (Z), Z โ† Z + 1 None 3

ELPM Extended Load Program Memory R0 โ† (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd โ† (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post-Increment

Rd โ† (RAMPZ:Z), Z โ† Z + 1 None 3

SPM Store Program Memory (Z) โ† R1:R0 None - ESPM Extended Store Program Memory

(RAMPZ:Z) โ† R1:R0 None -

IN Rd, A In From I/O Location Rd โ† I/O(A) None 1 OUT A, Rr Out To I/O Location I/O(A) โ† Rr None 1 PUSH Rr Push Register on Stack STACK โ† Rr None 2 POP Rd Pop Register from Stack Rd โ† STACK None 2 Bit and Bit-test Instructions LSL Rd Logical Shift Left Rd(n+1)โ†Rd(n),Rd(0)โ†0,Cโ†Rd(7) Z,C,N,V,H 1 LSR Rd Logical Shift Right Rd(n)โ†Rd(n+1),Rd(7)โ†0,Cโ†Rd(0) Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)โ†C,Rd(n+1)โ†Rd(n),Cโ†Rd(7) Z,C,N,V,H 1 ROR Rd Rotate Right Through Carry Rd(7)โ†C,Rd(n)โ†Rd(n+1),Cโ†Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) โ† Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) โ†” Rd(7..4) None 1 BSET s Flag Set SREG(s) โ† 1 SREG(s) 1 BCLR s Flag Clear SREG(s) โ† 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) โ† 1 None 2 CBI A, b Clear Bit in I/O Register I/O(A, b) โ† 0 None 2 BST Rr, b Bit Store from Register to T T โ† Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) โ† T None 1 SEC Set Carry C โ† 1 C 1 CLC Clear Carry C โ† 0 C 1 SEN Set Negative Flag N โ† 1 N 1 CLN Clear Negative Flag N โ† 0 N 1 SEZ Set Zero Flag Z โ† 1 Z 1 CLZ Clear Zero Flag Z โ† 0 Z 1

Instruction Set Summary (Continued)

Mnemonics Operands Description Operation Flags #Clock Note

8 Instruction Set

SEI Global Interrupt Enable I โ† 1 I 1 CLI Global Interrupt Disable I โ† 0 I 1 SES Set Signed Test Flag S โ† 1 S 1 CLS Clear Signed Test Flag S โ† 0 S 1 SEV Set Twoโ€™s Complement Overflow V โ† 1 V 1 CLV Clear Twoโ€™s Complement Overflow

V โ† 0 V 1

SET Set T in SREG T โ† 1 T 1 CLT Clear T in SREG T โ† 0 T 1 SEH Set Half Carry Flag in SREG H โ† 1 H 1 CLH Clear Half Carry Flag in SREG H โ† 0 H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1

Instruction Set Summary (Continued)

Mnemonics Operands Description Operation Flags #Clock Note