Computer Architecture: Instruction Execution and Data Transfer, Lecture notes of Computer Architecture and Organization

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Chapter

Dr. Bernard Chen Ph.D.

University of Central Arkansas

Spring 2009

Purpose of This Chapter



In this chapter we introduce a

basic computer and show how its

operation can be specified with

register transfer statements.

Program statements and

computer instructions

Computer instruction

Field specifying the

operation to be executed

Field specifying the data

To be operated on

5

Instruction code format



Instruction code format with two

parts : Op. Code + Address



Op. Code : specify 16 possible operations(

bits)



Address : specify the address of an

operand(12 bits)



If an operation in an instruction code does not

need an operand from memory, the rest of

the bits in the instruction( address field ) can

be used for other purpose

Op. Code Address 15 12 11 0 instruction data 15 12 11 0 Not an instruction

Number of Operands per

instruction

 (^) No Operands HALT NOP  (^) 1 operand NOT R4 R4  R  (^) 2 operands ADD R1, R2 R1  R1 + R  (^) 3 operands ADD R1, R2, R3 R1  R2 + R  (^) > 3 operands MADD R4,R1,R2,R3 R4  R1+(R2*R3)  (^) Each specify one operation and 1,2, 3 or 4 data locations.

Instructions are read from memory as words  Instructions can be formatted to fit in one or more memory words.  An instruction may contain 

An opcode + data (immediate operand)



An opcode + the address of data (direct addressing)



An opcode + an address where the address of the

data is found (indirect addressing)

 Data only (location has no instructions)

 An opcode only (register-reference or input/output

instruction)

The address register is connected to the memory

1. Program Counter Increments by units of addresses 0 0 0 0 0 0 0 1 PC

000000000010

2. The next address is put on the bus and is loaded into the Address Register AR 000000000010
3. The Bits of the AR are wired directly to the RAM Address lines to enable loading the memory into the Instruction R. Direct access to Memory IR (^1010101010101010) The Program Counter points to the next address of the program

Direct address

2. Address is selected in memory and its Data placed on the bus to be loaded into the Data Register to be used for requested instructions Occurs When the Operand Part Contains the Address of Needed Data.
3. Address part of IR is placed on the bus and loaded back into the AR

Indirect address

3. New Address is selected in memory and placed on the bus to be loaded into the DR to use later
4. Address is selected in memory and placed on the bus to be loaded Back into the AR Occurs When the Operand Contains the Address of the Address of Needed Data.
5. Address part of IR is placed on the bus and loaded back into the AR

Indirect address

Direct and Indirect addressing example Addressing Mode

17 Bus s 0 s 1 s 2 16-bit common bus Clock LD LD LD INR OUTR IR INPR LD INR CLR LD (^) INR CLR LD (^) INR CLR LD INR CLR WRITE Address Adder & Logic E DR PC AR CLR 7 1 2 3 4 5 6 Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc. AC Mano’s Computer Figure 5- READ Memory Unit 4096x TR

5-2 Computer Registers

 (^) Data Register( DR ) : hold the operand(Data) read from memory  Accumulator Register( AC ) : general purpose processing register  (^) Instruction Register( IR ) : hold the instruction read from memory  (^) Temporary Register( TR ) : hold a temporary data during processing  Address Register( AR ) : hold a memory address, 12 bit w idth

5-2 Computer Registers

 Program Counter( PC ) :  (^) hold the address of the next instruction to be read fro m memory after the current instruction is executed  (^) Instruction words are read and executed in sequence u nless a branch instruction is encountered  (^) A branch instruction calls for a transfer to a nonconsec utive instruction in the program  (^) The address part of a branch instruction is transferred to PC to become the address of the next instruction  To read instruction, memory read cycle is initiated, and PC is incremented by one(next instruction fetch)