Basic Modeling Constructs - Computer-Aided Circuit Design - Lecture Slides, Slides of Computer Science

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Basic Modeling Constructs

Entity Declaration

• EBNF: see page 108

• Example:

entity adder is port ( a : in word; b : in word; sum : out word ); end entity adder; entity adder is port ( a, b : in word; sum : out word ); end entity adder;

library ieee; use ieee.std_logic_1164.all; entity program_ROM is port ( address : in std_ulogic_vector(14 downto 0); data : out std_ulogic_vector(7 downto 0); enable : in std_ulogic ); subtype instruction_byte is bit_vector(7 downto 0); type program_array is array (0 to 2**14 - 1) of instruction_byte; constant program : program_array := ( X"32", X"3F", X"03", -- LDA $3F X"71", X"23", -- BLT $ others => X"00" --... ); end entity program_ROM;

Architecture Bodies

• Architecture bodies describe the internal operations of modules
• EBNF: see 110
• Example: architecture abstract of adder is begin add_a_b : process (a, b) is begin sum <= a + b; end process add_a_b; end architecture abstract;

Signal Declarations

• EBNF: see page 111

• Example: next page

architecture primitive of and_or_inv is signal and_a, and_b : bit; signal or_a_b : bit; begin and_gate_a : process (a1, a2) is begin and_a <= a1 and a2; end process and_gate_a; and_gate_b : process (b1, b2) is begin and_b <= b1 and b2; end process and_gate_b; or_gate : process (and_a, and_b) is begin or_a_b <= and_a or and_b; end process or_gate; inv : process (or_a_b) is begin y <= not or_a_b; end process inv; end architecture primitive;

Signal Assignment

• Clock generator:

clock_gen : process (clk) is

begin

if clk = '0' then

clk <= '1' after T_pw, '0' after 2*T_pw;

end if;

end process clock_gen;

Signal Assignment

• Two-input multiplexer

mux : process (a, b, sel) is begin case sel is when '0' => z <= a after prop_delay; when '1' => z <= b after prop_delay; end case; end process mux;

Signal Attributes

• Given a signal S and a value T of type time

• S’event: true if there is an event on S in the

current simulation cycle

• S’active: true if there is a transaction on S in the

current simulation cycle

• S’last_event: the time interval since the last event

on S

• S’last_active: the time interval since the last

transaction on S

• S’last_value: the value of S just before the last

event on S

Signal Attributes

• Example: check setup time requirement

if clk'event and (clk = '1' or clk = 'H') and (clk'last_value = '0' or clk'last_value = 'L') then assert d'last_event >= Tsu report "Timing error: d changed within setup time of clk"; end if;

Wait Statements

• EBNF: see page 118

• Wait statement causes the process to suspend

execution

• Sensitivity clause: on signal_names

• Condition clause: until boolean_expression

• Timeout clause: for time_expression

Wait Statements

• Example:

half_add : process is

begin

sum <= a xor b after T_pd;

carry <= a and b after T_pd;

wait on a, b;

end process half_add Docsity.com

entity mux2 is

port ( a, b, sel : in bit; z : out bit );

end entity mux2;

---

architecture behavioral of mux2 is

constant prop_delay : time := 2 ns;

begin

slick_mux : process is begin case sel is when '0' => z <= a after prop_delay; wait on sel, a; when '1' => z <= b after prop_delay; wait on sel, b; end case; end process slick_mux;

end architecture behavioral; Docsity.com

Wait Statements

• Example

wait until clk = ‘1’;

Cause the executing process to suspend until the

value of the signal clk changes to ‘1’

• Note that if the wait statement does not include a

sensitivity clause, the condition is tested

whenever an event occurs on any of the signals

mentioned in the condition

• wait on clk until reset=‘0’; reset is tested when clk

change