Pentium Instructions: EFLAGS, Operands, and Arithmetic/Logic Operations, Study notes of Computer Science

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Basic Pentium InstructionsBasic Pentium Instructions

October 18October 18

CSC201 Section 002

Fall, 2000

The EFLAGS Register The EFLAGS Register

• Bit 11 = Overflow Flag
• Bit 7 = Sign Flag
• Bit 6 = Zero Flag
• Bit 0 = Carry Flag
• "Sets the flags" means sets OF, ZF,

SF, CF in the "normal" way

"mov "mov" Instruction" Instruction

• Operand combinations: reg/mem,

reg/imm

• Another combination: reg, mem
• 8-bit versions of all of the above
• No effect on flags

"mov EAX, myvar"

"mov EAX, EBX" "mov EAX, 0A34H" "mov [EBP+4], EAX" "mov myvar, 022334455h"

"movsx "movsx" and "" and "movzxmovzx" Instructions" Instructions

• Operands combination: reg,

reg8/mem

• No effect on flags

"movsx EAX, BL" "movsx EAX, mychar1"

Push and Pop Push and Pop

• Push
  • Operand combination: reg/mem/imm
  • Can also push a byte-length immediate
• Pop
  • Operand combination: reg/mem
  • Cannot pop byte-length operands

“push EAX” “push [ESI+4]” “push 22AAFF33h”

“pop EAX” “pop myvar”

"add" and "sub" Instructions "add" and "sub" Instructions

• Operands: reg/mem, reg/imm
• Another combination: reg, mem
• 8-bit versions of the above
• Setting of the flags...
  • Overflow detect (OF) assumes operands are twos-complement numbers
  • Unsigned overflow detect: use CF instead

"add myvar, ECX" "sub EBX, -22"

"add EAX, myvar"

"inc" and "sub" Instructions "inc" and "sub" Instructions

• Operand combination: reg/mem
  • Like "add operand, 1" and "sub operand, 1"
• 8-bit versions of the above
• Sets the flags
  • Overflow detect assumes operand is twos-complement number
  • Does not affect CF; unsigned overflow detect not possible

"neg "neg" Instruction" Instruction

• Two's-complement a number
• Operands: reg / mem
• 8-bit versions of the above
• Sets the flags

"neg EAX"

"imul "imul" Instruction" Instruction

• Signed multiply
• One-address, two-address, and

three-address formats!

• Operands: reg/mem
  • EDX:EAX <-- EAX * reg (or mem)
• Operands: reg, reg/mem
  • reg <-- reg * reg (or mem)

“mul EBX”

“mul EAX, myvar”

"imul "imul" Instruction" Instruction

• Operand combination: reg, reg/mem,

imm

• reg <-- reg (or mem) * imm
• (There is an 8-bit version we will not

use)

• Only useful flag: CF = 0 means result

fits in EAX alone (or destination

register), CF = 1 otherwise

“mul EAX, myvar, 55”

"idiv "idiv" Instruction" Instruction

• Signed divide
• Otherwise, same as "div"

"not" Instruction "not" Instruction

• operand: reg/mem
• 8-bit version also
• no effect on flags

"not [EAX+35]"

"shr "shr", "", "sarsar", "", "shlshl" and "" and "salsal"" InstructionsInstructions

• operands: reg/mem, cl/imm
• cl and imm8 should have a value

between 0 and 31

• shr does zero fill, sar does sign

extension

• shl and sar do same thing
• 8-bit versions also (but imm8 can

only = 1)

• affects ZF, SF, and CF
  • shr and sar: CF = least-significant-bit (before shifting)
  • shl and sal: CF = most-significant-bit (before shifting)

“sar dword ptr [EBP – 8], 1” “shr EAX, CL”

"rol "rol" and "" and "rorror" Instructions" Instructions

• operands: reg/mem, cl/imm
• cl and imm8 should have a value

between 0 and 31

• 8-bit versions also (but imm8 can

only = 1)

• affects ZF, SF, and CF
  • ror: CF = least-significant-bit (before shifting)
  • rol: CF = most-significant-bit (before shifting)

“ror dword ptr [EBX], 4” “rol EAX, CL”