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CHAPTER OBJECTIVES
● ● Become familiar with the r (^) e , hybrid, and hybrid p models for the BJT transistor. ● Learn to use the equivalent model to find the important ac parameters for an amplifier. ● Understand the effects of a source resistance and load resistor on the overall gain and characteristics of an amplifier. ● Become aware of the general ac characteristics of a variety of important BJT configurations. ● Begin to understand the advantages associated with the two-port systems approach to single- and multistage amplifiers. ● Develop some skill in troubleshooting ac amplifier networks.
5.1 INTRODUCTION
● The basic construction, appearance, and characteristics of the transistor were introduced in Chapter 3. The dc biasing of the device was then examined in detail in Chapter 4. We now begin to examine the ac response of the BJT amplifier by reviewing the models most fre- quently used to represent the transistor in the sinusoidal ac domain. One of our first concerns in the sinusoidal ac analysis of transistor networks is the mag- nitude of the input signal. It will determine whether small-signal or large-signal techniques should be applied. There is no set dividing line between the two, but the application—and the magnitude of the variables of interest relative to the scales of the device characteristics— will usually make it quite clear which method is appropriate. The small-signal technique is introduced in this chapter, and large-signal applications are examined in Chapter 12. There are three models commonly used in the small-signal ac analysis of transistor networks: the re model, the hybrid p model, and the hybrid equivalent model. This chapter introduces all three but emphasizes the re model.
5.2 AMPLIFICATION IN THE AC DOMAIN
● It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device. That is, the output sinusoidal signal is greater than the input sinusoidal signal, or, stated another way, the output ac power is greater than the input ac power. The question then arises as to how the ac power output can be greater than the input ac power. Conservation of energy dictates that over time the total power output, Po , of a system cannot be greater than its power
BJT AC Analysis
input, Pi , and that the efficiency defined by h = Po > Pi cannot be greater than 1. The factor missing from the discussion above that permits an ac power output greater than the input ac power is the applied dc power. It is the principal contributor to the total output power even though part of it is dissipated by the device and resistive elements. In other words, there is an “exchange” of dc power to the ac domain that permits establishing a higher output ac power. In fact, a conversion efficiency is defined by h = Po (ac) > Pi (dc) , where Po (ac) is the ac power to the load and Pi (dc) is the dc power supplied. Perhaps the role of the dc supply can best be described by first considering the simple dc network of Fig. 5.1. The resulting direction of flow is indicated in the figure with a plot of the current i versus time. Let us now insert a control mechanism such as that shown in Fig. 5.2. The control mechanism is such that the application of a relatively small signal to the control mechanism can result in a substantial oscillation in the output circuit.
254^ BJT AC ANALYSIS
I dc I dc
I dc
I dc
I dc
E
R
i
0 t
FIG. 5. Steady current established by a dc supply.
i (^) T
i c
i (^) T (^) i T
iT
R (^) i (^) T = I dc + i ac
0 t
Control mechanism E
FIG. 5. Effect of a control element on the steady-state flow of the electrical system of Fig. 5.1.
That is, for this example, i ac(p@p) W ic (p@p) and amplification in the ac domain has been established. The peak-to-peak value of the output current far exceeds that of the control current. For the system of Fig. 5.2, the peak value of the oscillation in the output circuit is con- trolled by the established dc level. Any attempt to exceed the limit set by the dc level will result in a “clipping” (flattening) of the peak region at the high and low end of the output signal. In general, therefore, proper amplification design requires that the dc and ac com- ponents be sensitive to each other’s requirements and limitations. However, it is extremely helpful to realize that: The superposition theorem is applicable for the analysis and design of the dc and ac components of a BJT network, permitting the separation of the analysis of the dc and ac responses of the system. In other words, one can make a complete dc analysis of a system before considering the ac response. Once the dc analysis is complete, the ac response can be determined using a completely ac analysis. It happens, however, that one of the components appearing in the ac analysis of BJT networks will be determined by the dc conditions, so there is still an important link between the two types of analysis.
5.3 BJT TRANSISTOR MODELING
● The key to transistor small-signal analysis is the use of the equivalent circuits (models) to be introduced in this chapter. A model is a combination of circuit elements, properly chosen, that best approximates the actual behavior of a semiconductor device under specific operating conditions. Once the ac equivalent circuit is determined, the schematic symbol for the device can be replaced by this equivalent circuit and the basic methods of circuit analysis applied to determine the desired quantities of the network. In the formative years of transistor network analysis the hybrid equivalent network was employed the most frequently. Specification sheets included the parameters in their listing, and analysis was simply a matter of inserting the equivalent circuit with the listed values.
256 BJT AC ANALYSIS
It is important as you progress through the modifications of the network to define the ac equivalent that the parameters of interest such as Z (^) i , Z (^) o , Ii , and Io as defined by Fig. 5.5 be carried through properly. Even though the network appearance may change, you want to be sure the quantities you find in the reduced network are the same as defined by the original network. In both networks the input impedance is defined from base to ground, the input current as the base current of the transistor, the output voltage as the voltage from collector to ground, and the output current as the current through the load resistor RC.
Ii
Io
Z (^) i
Z (^) o Vo
Vi
FIG. 5. The network of Fig. 5.3 following removal of the dc supply and insertion of the short-circuit equivalent for the capacitors.
Ii
Zi
I (^) o
Zo Vi Vo
- –
System
FIG. 5. Defining the important parameters of any system.
I (^) i Io
V (^) i Vo
Ri Ro
FIG. 5. Demonstrating the reason for the defined directions and polarities.
The parameters of Fig. 5.5 can be applied to any system whether it has one or a thou- sand components. For all the analysis to follow in this text, the directions of the currents, the polarities of the voltages, and the direction of interest for the impedance levels are as appearing in Fig. 5.5. In other words, the input current I (^) i and output current Io are, by defini- tion, defined to enter the system. If, in a particular example, the output current is leaving the system rather than entering the system as shown in Fig. 5.5, a minus sign must be applied. The defined polarities for the input and output voltages are also as appearing in Fig. 5.5. If V (^) o has the opposite polarity, the minus sign must be applied. Note that Zi is the impedance “looking into” the system, whereas Zo is the impedance “looking back into” the system from the output side. By choosing the defined directions for the currents and voltages as appearing in Fig. 5.5, both the input impedance and output impedance are defined as having positive values. For example, in Fig. 5.6 the input and output impedances for a particular system are both resistive. For the direction of I (^) i and Io the resulting voltage across the resis- tive elements will have the same polarity as Vi and Vo , respectively. If I (^) o had been defined as the opposite direction in Fig. 5.5 a minus sign would have to be applied. For each case Z (^) i = Vi > Ii and Z (^) o = Vo > Io with positive results if they all have the defined directions and polarity of Fig. 5.5. If the output current of an actual system has a direction opposite to that
THE r (^) e TRANSISTOR 257 MODEL
of Fig. 5.5 a minus sign must be applied to the result because Vo must be defined as appear- ing in Fig. 5.5. Keep Fig. 5.5 in mind as you analyze the BJT networks in this chapter. It is an important introduction to “System Analysis,” which is becoming so important with the expanded use of packaged IC systems. If we establish a common ground and rearrange the elements of Fig. 5.4, R 1 and R 2 will be in parallel, and R (^) C will appear from collector to emitter as shown in Fig. 5.7. Because the components of the transistor equivalent circuit appearing in Fig. 5.7 employ familiar components such as resistors and independent controlled sources, analysis techniques such as superposition, Thévenin’s theorem, and so on, can be applied to determine the desired quantities.
B
Ii
Z (^) i
FIG. 5. Circuit of Fig. 5.4 redrawn for small-signal ac analysis.
V (^) i
V (^) be
B
C
E Ie
Ib
FIG. 5. Finding the input equivalent circuit for a BJT transistor.
Let us further examine Fig. 5.7 and identify the important quantities to be determined for the system. Because we know that the transistor is an amplifying device, we would expect some indication of how the output voltage V (^) o is related to the input voltage V (^) i — the voltage gain. Note in Fig. 5.7 for this configuration that the current gain is defined by Ai = Io > Ii. In summary, therefore, the ac equivalent of a transistor network is obtained by:
**_1. Setting all dc sources to zero and replacing them by a short-circuit equivalent
- Replacing all capacitors by a short-circuit equivalent
- Removing all elements bypassed by the short-circuit equivalents introduced by steps_** **_1 and 2
- Redrawing the network in a more convenient and logical form_** In the sections to follow, a transistor equivalent model will be introduced to complete the ac analysis of the network of Fig. 5.7.
5.4 THE re TRANSISTOR MODEL
● The re model for the CE, CB, and CC BJT transistor configurations will now be introduced with a short description of why each is a good approximation to the actual behavior of a BJT transistor.
Common-Emitter Configuration
The equivalent circuit for the common-emitter configuration will be constructed using the device characteristics and a number of approximations. Starting with the input side, we find the applied voltage Vi is equal to the voltage Vbe with the input current being the base cur- rent Ib as shown in Fig. 5.8. Recall from Chapter 3 that because the current through the forward-biased junction of the transistor is IE , the characteristics for the input side appear as shown in Fig. 5.9a for various levels of VBE. Taking the average value for the curves of Fig. 5.9a will result in the single curve of Fig. 5.9b, which is simply that of a forward-biased diode.
THE r (^) e TRANSISTOR 259 MODEL
The result is that the impedance seen “looking into” the base of the network is a resistor equal to beta times the value of re , as shown in Fig. 5.14. The collector output current is still linked to the input current by beta as shown in the same figure.
β r (^) e Ib
Ic
β
I (^) b b
e
c
e
FIG. 5. Improved BJT equivalent circuit.
VA^0 VCEQ VA + VCEQ
VCE (V)
Slope = (^) r^1 o 2
Slope = (^) r^1 o (^1) Δ IC
Δ IC
Δ VCE
Δ VCE
IC (mA)
ICQ
FIG. 5. Defining the Early voltage and the output impedance of a transistor.
The equivalent circuit has therefore been defined for the ideal characteristics of Fig. 5.11, but now the input and output circuits are isolated and only linked by the controlled source—a form much easier to work with when analyzing networks.
Early Voltage
We now have a good representation for the input circuit, but aside from the collector out- put current being defined by the level of beta and IB , we do not have a good representation for the output impedance of the device. In reality the characteristics do not have the ideal appearance of Fig. 5.11. Rather, they have a slope as shown In Fig. 5.15 that defines the output impedance of the device. The steeper the slope, the less the output impedance and the less ideal the transistor. In general, it is desirable to have large output impedances to avoid loading down the next stage of a design. If the slope of the curves is extended until they reach the horizontal axis, it is interesting to note in Fig. 5.15 that they will all intersect at a voltage called the Early voltage. This intersection was first discovered by James M. Early in 1952. As the base current increases the slope of the line increases, resulting in an increase in output impedance with increase in base and collector current. For a particular collector and base current as shown in Fig. 5.15, the output impedance can be found using the following equation:
r (^) o =
V
I
VA + VCEQ
ICQ
260 BJT AC ANALYSIS Typically, however, the Early voltage is sufficiently large compared with the applied collector-to-emitter voltage to permit the following approximation.
r (^) o
VA
ICQ
Clearly, since V (^) A is a fixed voltage, the larger the collector current, the less the output impedance. For situations where the Early voltage is not available the output impedance can be found from the characteristics at any base or collector current using the following equation:
Slope =
y x
IC
VCE
r (^) o
and r (^) o =
VCE
IC
For the same change in voltage in Fig. 5.15 the resulting change in current ¢ IC is signifi- cantly less for r (^) o 2 than r (^) o 1 , resulting in r (^) o 2 being much larger than r (^) o 1. In situations where the specification sheets of a transistor do not include the Early volt- age or the output characteristics, the output impedance can be determined from the hybrid parameter hoe that is normally plotted on every specification sheet. It is a quantity that will be described in detail in Section 5.19. In any event, an output impedance can now be defined that will appear as a resistor in parallel with the output as shown in the equivalent circuit of Fig. 5.16.
FIG. 5. re model for the common-emitter transistor configuration including effects of ro.
The equivalent circuit of Fig. 5.16 will be used throughout the analysis to follow for the common-emitter configuration. Typical values of beta run from 50 to 200, with values of b re typically running from a few hundred ohms to a maximum of 6 k to 7 k. The output resistance r is typically in the range of 40 k to 50 k.
Common-Base Configuration
The common-base equivalent circuit will be developed in much the same manner as applied to the common-emitter configuration. The general characteristics of the input and output circuit will generate an equivalent circuit that will approximate the actual behavior of the device. Recall for the common-emitter configuration the use of a diode to represent the connection from base to emitter. For the common-base configuration of Fig. 5.17a the pnp transistor employed will present the same possibility at the input circuit. The result is the use of a diode in the equivalent circuit as shown in Fig. 5.17b. For the output circuit, if we return to Chapter 3 and review Fig. 3.8, we find that the collector current is related to the emitter current by alpha a. In this case, however, the controlled source defining the collector current as inserted in Fig. 5.17b is opposite in direction to that of the controlled source of the common-emitter configuration. The direction of the collector current in the output circuit is now opposite that of the defined output current.
262 BJT AC ANALYSIS Common-Collector Configuration
For the common-collector configuration, the model defined for the common-emitter configu- ration of Fig. 5.16 is normally applied rather than defining a model for the common-collector configuration. In subsequent chapters, a number of common-collector configurations will be investigated, and the effect of using the same model will become quite apparent.
npn versus pnp
The dc analysis of npn and pnp configurations is quite different in the sense that the currents will have opposite directions and the voltages opposite polarities. However, for an ac analy- sis where the signal will progress between positive and negative values, the ac equivalent circuit will be the same.
5.5 COMMON-EMITTER FIXED-BIAS
CONFIGURATION
● The transistor models just introduced will now be used to perform a small-signal ac analy- sis of a number of standard transistor network configurations. The networks analyzed rep- resent the majority of those appearing in practice. Modifications of the standard configurations will be relatively easy to examine once the content of this chapter is reviewed and understood. For each configuration, the effect of an output impedance is examined for completeness. The computer analysis section includes a brief description of the transistor model em- ployed in the PSpice and Multisim software packages. It demonstrates the range and depth of the available computer analysis systems and how relatively easy it is to enter a complex network and print out the desired results. The first configuration to be analyzed in detail is the common-emitter fixed-bias network of Fig. 5.20. Note that the input signal V (^) i is applied to the base of the transistor, whereas the output Vo is off the collector. In addition, recognize that the input current I (^) i is not the base current, but the source current, and the output current Io is the collector current. The small-signal ac analysis begins by removing the dc effects of VCC and replacing the dc blocking capacitors C 1 and C 2 by short-circuit equivalents, resulting in the network of Fig. 5.21.
RB
RC
Vo
VCC
C 2
I (^) o
Z (^) o
Zi
C 1
Vi
Ii B
C
E
FIG. 5. Common-emitter fixed-bias configuration.
Vo Ii Io
R (^) C R (^) B
B
C
E
Z (^) o Z (^) i
V (^) i
FIG. 5. Network of Fig. 5.20 following the removal of the effects of VCC, C 1 , and C 2_._
Note in Fig. 5.21 that the common ground of the dc supply and the transistor emitter terminal permits the relocation of RB and RC in parallel with the input and output sections of the transistor, respectively. In addition, note the placement of the important network parameters Z (^) i , Zo , I (^) i , and Io on the redrawn network. Substituting the r (^) e model for the common-emitter configuration of Fig. 5.21 results in the network of Fig. 5.22. The next step is to determine b, re , and r (^) o. The magnitude of b is typically obtained from a specification sheet or by direct measurement using a curve tracer or transistor
COMMON-EMITTER 263
FIXED-BIAS CONFIGURATION
testing instrument. The value of r (^) e must be determined from a dc analysis of the system, and the magnitude of r (^) o is typically obtained from the specification sheet or characteristics. Assuming that b, r (^) e , and r (^) o have been determined will result in the following equations for the important two-port characteristics of the system.
Zi Figure 5.22 clearly shows that
Z i = RB 7 b r e ohms (5.5)
For the majority of situations RB is greater than b re by more than a factor of 10 (recall from the analysis of parallel elements that the total resistance of two parallel resistors is always less than the smallest and very close to the smallest if one is much larger than the other), permitting the following approximation:
Z (^) i b r (^) e RB Ú 10 b r (^) e
ohms (5.6)
Z (^) o Recall that the output impedance of any system is defined as the impedance Z (^) o determined when V (^) i 0. For Fig. 5.22, when V (^) i 0, Ii = Ib = 0, resulting in an open- circuit equivalence for the current source. The result is the configuration of Fig. 5.23. We have
Z o = RC 7 r o ohms (5.7)
If r o Ú 10 RC , the approximation RC 7 r o RC is frequently applied, and
Z (^) o RC ro Ú 10 RC
Av The resistors r (^) o and RC are in parallel, and
Vo = - b Ib ( RC 7 r o )
but Ib =
Vi b r (^) e
so that Vo = - ba
Vi b r (^) e
b( RC 7 r o )
and Av =
Vo Vi
( RC 7 r o )
r (^) e
If r (^) o Ú 10 RC , so that the effect of ro can be ignored,
Av = -
RC
r (^) e r (^) o Ú 10 RC
Note the explicit absence of b in Eqs. (5.9) and (5.10), although we recognize that b must be utilized to determine re.
I (^) b Ic
b c
β Ib
I (^) i
Io Vo
Zo
RB RC
Zi Vi (^) r β (^) e ro
FIG. 5. Substituting the re model into the network of Fig. 5.21.
Zo ro RC
FIG. 5. Determining Zo for the network of Fig. 5.22.
e. Z o = r o^7 RC = 50 k 7 3 k = 2.83 k vs. 3 k VOLTAGE-DIVIDER BIAS^265
Av = -
r o 7 RC
r (^) e
2.83 k 10.71
= 264.24 vs. - 280.
5.6 VOLTAGE-DIVIDER BIAS
● The next configuration to be analyzed is the voltage-divider bias network of Fig. 5.26. Recall that the name of the configuration is a result of the voltage-divider bias at the input side to determine the dc level of VB. Substituting the re equivalent circuit results in the network of Fig. 5.27. Note the absence of RE due to the low-impedance shorting effect of the bypass capacitor, CE. That is, at the frequency (or frequencies) of operation, the reactance of the capacitor is so small compared to RE that it is treated as a short circuit across RE. When VCC is set to zero, it places one end of R 1 and RC at ground potential as shown in Fig. 5.27. In addition, note that R 1 and R 2 remain part of the input circuit, whereas RC is part of the output circuit. The parallel combination of R 1 and R 2 is defined by
R = R 1 7 R 2 =
R 1 R 2
R 1 + R 2
Zi From Fig. 5.
Z i = R 7 b r e (5.12)
VCC
C 1
CE
Vi
I (^) o
Ii
R (^) C
C 2
Z (^) o
R (^) E
Zi R 2
B
C
E
R 1 Vo
FIG. 5. Voltage-divider bias configuration.
β Ib
Ib I (^) o
R'
Ii
b c
e e
Vi Zi R 1 R 2 β re ro R (^) C Vo Zo
FIG. 5. Substituting the re equivalent circuit into the ac equivalent network of Fig. 5.26.
266 BJT AC ANALYSIS Zo From Fig. 5.27 with^ Vi set to 0 V, resulting in^ Ib =^0 mA and^ b Ib =^0 mA,
Z o = RC^7 r o (5.13)
If r (^) o Ú 10 RC ,
Z (^) o RC ro Ú 10 RC
Av Because RC and ro are in parallel,
Vo = - (b Ib )( RC^7 r o )
and Ib =
Vi b r (^) e
so that Vo = - ba
Vi b r (^) e
b( RC^7 r o )
and Av =
Vo Vi
which you will note is an exact duplicate of the equation obtained for the fixed-bias con- figuration. For r (^) o Ú 10 RC ,
Av =
Vo Vi
RC
r (^) e r (^) o Ú 10 RC
Phase Relationship The negative sign of Eq. (5.15) reveals a 180° phase shift between V (^) o and Vi.
EXAMPLE 5.2 For the network of Fig. 5.28, determine: a. re. b. Zi. c. Zo ( r (^) o = ). d. Av ( r (^) o = ). e. The parameters of parts (b) through (d) if r (^) o = 50 k and compare results.
Vi β= 90^ Z^ o
22 V
6.8 kΩ 10 F
1.5 kΩ
8.2 kΩ
56 kΩ
Zi
I (^) i
I (^) o
Vo
μ
10 μF
20 μF
FIG. 5. Example 5.2.
268 BJT AC ANALYSIS most situations its effect can be ignored, it will not be included in the present analysis. However, the effect of r (^) o will be discussed later in this section. Applying Kirchhoff’s voltage law to the input side of Fig. 5.30 results in Vi = Ib b r (^) e + IeRE or Vi = Ib b r (^) e + (b + I ) Ib RE and the input impedance looking into the network to the right of R (^) B is
Z (^) b =
Vi Ib
= b r (^) e + (b + 1) RE
The result as displayed in Fig. 5.31 reveals that the input impedance of a transistor with an unbypassed resistor RE is determined by
Z b = b r e + (b + 1) RE (5.17)
Because b is normally much greater than 1, the approximate equation is Z (^) b b r (^) e + b RE
and Z b b( r e + RE ) (5.18)
Because RE is usually greater than re , Eq. (5.18) can be further reduced to
Z b b RE (5.19)
Zi Returning to Fig. 5.30, we have
Z i = RB 7 Z b (5.20)
Zo With V (^) i set to zero, Ib = 0, and b Ib can be replaced by an open-circuit equivalent. The result is
Z o = RC (5.21)
Av
Ib =
Vi Z (^) b and Vo = - Io RC = - b Ib RC
= - ba
Vi Z (^) b
b RC
with Av =
Vo Vi
b RC Z (^) b
Substituting Z (^) b b( r (^) e + RE ) gives
Av =
Vo Vi
RC
r (^) e + RE
and for the approximation Z (^) b b RE ,
Av =
Vo Vi
RC
RE
Note the absence of b from the equation for A (^) v demonstrating an independence in variation of b.
Phase Relationship The negative sign in Eq. (5.22) again reveals a 180° phase shift between Vo and Vi.
Zb RE
re^ β
FIG. 5. Defining the input impedance of a transistor with an unbypassed emitter resistor.
CE EMITTER-BIAS 269
CONFIGURATION
Effect of ro The equations appearing below will clearly reveal the additional complexity resulting from including r (^) o in the analysis. Note in each case, however, that when certain conditions are met, the equations return to the form just derived. The derivation of each equation is beyond the needs of this text and is left as an exercise for the reader. Each equation can be derived through careful application of the basic laws of circuit analysis such as Kirchhoff’s voltage and current laws, source conversions, Thévenin’s theorem, and so on. The equations were included to remove the nagging question of the effect of r (^) o on the important parameters of a transistor configuration.
Zi
Z (^) b = b r (^) e + c
(b + 1) + RC > r (^) o 1 + ( RC + RE )> r (^) o
d RE (5.25)
Because the ratio RC > r (^) o is always much less than (b + 1),
Z (^) b b r (^) e +
(b + 1) RE 1 + ( RC + RE )> r (^) o For r (^) o Ú 10( RC + RE ), Z (^) b b r (^) e + (b + 1) RE which compares directly with Eq. (5.17). In other words, if r (^) o Ú 10( RC + RE ), all the equations derived earlier result. Because b + 1 b, the following equation is an excellent one for most applications:
Z (^) b b( r (^) e + RE ) (^) r o Ú^ 10( RC +^ RE )^
Zo
Z o = RC £ r o +
b( r (^) o + r (^) e )
1 +
b r (^) e RE
However, r (^) o W r (^) e , and
Z o RC r o £ 1 +
b
1 +
b r (^) e RE
which can be written as
Z o RC r o £ 1 +
b
r (^) e RE
Typically 1>b and r (^) e > RE are less than one with a sum usually less than one. The result is a multiplying factor for ro greater than one. For b = 100, r (^) e = 10 , and RE = 1 k, 1 1 b
r (^) e RE
and Z o = RC^7 51 r o
which is certainly simply RC. Therefore,
Z (^) o RC Any level of r (^) o
which was obtained earlier.
CE EMITTER-BIAS 271
CONFIGURATION
b. Testing the condition r (^) o Ú 10( RC + RE ), we obtain 40 k Ú 10(2.2 k + 0.56 k) 40 k Ú 10(2.76 k) = 27.6 k ( satisfied ) Therefore, Z (^) b b( r (^) e + RE ) = 120(5.99 + 560 ) = 67.92 k
and Z i = RB 7 Z b = 470 k 7 67.92 k
= 59.34 k c. Z (^) o = RC = 2.2 k d. r (^) o Ú 10 RC is satisfied. Therefore,
Av =
Vo Vi
b RC Z (^) b
(120)(2.2 k) 67.92 k = 3. compared to - 3.93 using Eq. (5.20): Av - RC > RE.
EXAMPLE 5.4 Repeat the analysis of Example 5.3 with CE in place.
Solution:
a. The dc analysis is the same, and r (^) e = 5.99 . b. R (^) E is “shorted out” by C (^) E for the ac analysis. Therefore,
Z i = RB 7 Z b = RB 7 b r e = 470 k 7 (120)(5.99 )
= 470 k 7 718.8 717.70
c. Z (^) o = RC = 2.2 k
d. Av = -
RC
r (^) e
= -
2.2 k 5.99
= 367.28 (a significant increase)
EXAMPLE 5.5 For the network of Fig. 5.33 (with C (^) E unconnected), determine (using appropriate approximations):
a. re. b. Zi. c. Zo. d. Av.
C 2
2.2 kΩ
CE
Z (^) o
0.68 kΩ
16 V
β = 210, ro = 50 kΩ
10 kΩ
90 kΩ
C 1 Vo
Vi
Zi
I (^) o
I (^) i
FIG. 5. Example 5.5.
272 BJT AC ANALYSIS Solution:
a. Testing b RE 7 10 R 2 , (210)(0.68 k) 7 10(10 k) 142.8 k 7 100 k ( satisfied ) we have
VB =
R 2
R 1 + R 2
VCC =
10 k 90 k + 10 k
(16 V) = 1.6 V
VE = VB - VBE = 1.6 V - 0.7 V = 0.9 V
IE =
VE
RE
0.9 V
0.68 k
= 1.324 mA
r (^) e =
26 mV IE
26 mV 1.324 mA
b. The ac equivalent circuit is provided in Fig. 5.34. The resulting configuration is differ- ent from Fig. 5.30 only by the fact that now
RB = R = R 1 7 R 2 = 9 k
R'
Io
2.2 kΩ 0.68 kΩ Vi 10 kΩ^ 90 kΩ
Z (^) o Vo
Zi
Ii
FIG. 5. The ac equivalent circuit of Fig. 5.33.
The testing conditions of r (^) o Ú 10( RC + RE ) and r (^) o Ú 10 RC are both satisfied. Using the appropriate approximations yields Z (^) b b RE = 142.8 k
Z i = RB 7 Z b = 9 k 7 142.8 k
= 8. 47 k c. Z (^) o = RC = 2.2 k
d. Av = -
RC
RE
2.2 k 0.68 k
EXAMPLE 5.6 Repeat Example 5.5 with C (^) E in place. Solution: a. The dc analysis is the same, and r (^) e = 19.64 . b. Z (^) b = b r (^) e = (210)(19.64 ) 4.12 k
Z i = RB 7 Z b = 9 k 7 4.12 k
= 2.83 k c. Z (^) o = RC = 2.2 k
d. Av = -
RC
r (^) e
2.2 k 19.64
= 112.02 (a significant increase)
Another variation of an emitter-bias configuration is shown in Fig. 5.35. For the dc analysis, the emitter resistance is RE 1 + RE 2 , whereas for the ac analysis, the resistor R (^) E in the equations above is simply RE 1 with RE 2 bypassed by CE.
