Boolean Function - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this exam paper are: Boolean Function, Space Provided, Computer Engineering, Sheet of Paper, Transistor Logic, Transistor-To-Transistor, Voltage Ranges, Output Voltage, Computer Design, Hexadecimal and Octal

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STUDENT NAME and NUMBER: (PLEASE PRINT CLEARLY)
REMARKS: 1. All questions should be answered (in the space provided).
2. Books and notes may NOT be used, with the exception of one 8.5”x11” sheet of paper.
DATE: June 11, 2001 TIME: 12:00 p.m. - 1:10 p.m.
Marks:
Total:
Q1
Q2
Q3
Q4
v. 1.0 - 1 of 5 -
Georgia Institute of Technology
Department of Electrical and Computer Engineering
Test #1
ECE2030: Introduction to Computer Engineering Q5
1. COMPUTER SYSTEMS (MAX MARK: 15)
a) The diagram below shows output voltage ranges for typical TTL (transistor-to-transistor logic). Describe
the purpose for the three voltage ranges for computer design and give some justification for their size.
b) Convert the following radix-2 number (binary number) to hexadecimal and octal.
1011011011.011012 ->
c) Expand the following hexadecimal number to decimal?
F5A.616 ->
VHmax
VHmin
VLmin
VLmax
5.5 V
4.0 V
1.0 V
-0.5 V
2
3
1Region 1 is for the logic level 1 and region 3 for logic level 0.
Region 2 is a zone that separates the other two regions so that
noise or voltage variations will not make a logic level 1 a 0 or a
logic level 0 a 1. The size of the voltage ranges allow the
introduction of small signal noise or voltage variations without
affecting the measured logic level.
hexadecimal
octal
2DB.6816
1333.328
3930.37510
/100
/15
/10
/25
/20
/30
pf3
pf4
pf5

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STUDENT NAME and NUMBER:

(PLEASE PRINT CLEARLY)

REMARKS: 1. All questions should be answered (in the space provided).

  1. Books and notes may NOT be used, with the exception of one 8.5”x11” sheet of paper.

DATE: June 11, 2001 TIME: 12:00 p.m. - 1:10 p.m.

Marks:

Total:

Q

Q

Q

Q

Georgia Institute of Technology

Department of Electrical and Computer Engineering

Test

ECE2030: Introduction to Computer Engineering

Q

1. COMPUTER SYSTEMS

(MAX MARK: 15)

a) The diagram below shows output voltage ranges for typical TTL (transistor-to-transistor logic). Describe

the purpose for the three voltage ranges for computer design and give some justification for their size.

b) Convert the following radix-2 number (binary number) to hexadecimal and octal.

2

->

c) Expand the following hexadecimal number to decimal?

F5A.

16

->

V

Hmax

V

Hmin

V

Lmin

V

Lmax

5.5 V

4.0 V

1.0 V

-0.5 V

2

3

1

Region 1 is for the logic level 1 and region 3 for logic level 0.

Region 2 is a zone that separates the other two regions so that

noise or voltage variations will not make a logic level 1 a 0 or a

logic level 0 a 1. The size of the voltage ranges allow the

introduction of small signal noise or voltage variations without

affecting the measured logic level.

hexadecimal

octal

2DB.

16

8

/

/

/

/

/

/

2. STANDARD FORMS (MAX MARK: 10)

Use Boolean algebra to expand the following Boolean function into a product-of-maxterms standard form.

Once expanded, express the Boolean function in -notation.

3. GATE DESIGN (MAX MARK: 25)

a) Extract the Boolean expressions for the outputs in the following gate diagram.

b) For the previous question, mark each gate with the number of transistors required to implement this gate

diagram using CMOS technology (i.e. nMOS and pMOS transistors).

What is the total number of transistors required?

M

F a b c( , , ) a b

( ) c

a b

( )c ac bc

ac b

( ) ac c

= ( a +b) ( b +c) ( )c = ( a + b +cc) ( aa + b +c) ( aa + bb +c)

= ( a + b +c) ( a + b +c) ( a + b +c) ( a + b +c) ( aa + bb +c)

= ( a + b +c) ( a + b +c) ( a + b +c) ( a + bb +c) ( a + bb +c)

= ( a + b +c) ( a + b +c) ( a + b +c) ( a + b +c) ( a + b +c)

M 0 1 3 5 7( , , , , )

A

B

F

C

D

E

G = F + ( BC) ⊕( D ⊕E) = A + ( BC)+( BC) ⊕( D ⊕E)

G

F = A +( BC)

8

8

2

2

0/2/

4

4

6

22 + 24 + 6 + 2*8 = 34 transistors without buffer

4. SWITCH NETWORKS (MAX MARK: 20)

For the expression below, create a switch level implementation using CMOS technology with nMOS and

pMOS transistors. Assume the inputs and their complements are available. Your design should contain no shorts

or floats. Use as few transistors as possible, but do not simplify the expression.

out = ( AB +AB) ( C +D E( +F)) +GH

D

F E

C

out

A

B

G H

A

B

G

H

A B

A B

D

E

F

C

5. KARNAUGH MAPS AND SIMPLIFICATION (MAX MARK: 30)

Shown below are two Karnaugh maps. The ‘X’s indicate “don’t cares” and should be used to form a mini-

mum number of prime implicants. For the following questions, circle and list ALL of the essential and non-

essential prime implicants. Also, write out ALL simplified Boolean functions of the form requested if more than

one simplified Boolean function exists for the Karnaugh map.

a) Given the following Karnaugh map, derive the simplified sum-of-products (SOP) expression.

b) Given the following Karnaugh map, derive the simplified product-of-sums (POS) expression.

prime implicants

essential?

yes no

AB

CD

00

01

11

10

00 01

11

10

C

A

B

D D D

B

B

C

A

F A B C D( , , , ) = ABC + AD + BC +AC

(SOP)

X=1 1

0 X=

ABD

AD

BC

AC

CD

F A B C D( , , , ) = ABC + AD + BC +CD

or

prime implicants

essential?

yes no

AB

CD

00

01

11

10

00 01

11

10

C

A

B

D D D

B

B

C

A

F A B C D( , , , ) = ( B +C) ( A + B +D) ( B + C +D)

(POS)

X=1 0

X=0 0

X=1 X=1 0

X=

A + B +D

B +C

B C D