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INTRODUCTION
In the world of microelectronics and VLSI,In the design flow of an ASIC or any printed circuit board containing the different components such as the microchips and the interconnects, there is always a term called testing and verification discussed, and it is one of the most important checkpoints in the design flow as a design engineer needs to check if the circuit that has been designed so far is correct or not, not just in terms of the output it is providing for different inputs but also in terms of not having any faults and problems in the internal circuitry. There are lots of techniques that have been discovered for testing and verification of VLSI circuits, some of these are: SCAN, Boundary SCAN Technique BIST (Built-In Self Test) ATPG (Automatic Test Pattern Generator) Boundary SCAN Technique: Definition and Components Boundary SCAN is a technique that allows us to probe the pin values of chips installed on PCBs without having to use a physical probe, so basically it is a technique that can be used to test the interconnects on a PCB i.e.
are the interconnects properly connected to the module that they are supposed to, and also this can be used to provide test inputs to a particular module on PCB. How the boundary SCAN Technique can be used is standardized using JTAG (Joint Test Action Group) Boundary SCAN Technique : Importance and Uses the Boundary SCAN technique can be used to test interconnects and sub-blocks inside an integrated circuit, it finds its application as debugging method for integrated circuits pin states. This technique is important as it realizes 2 very important concepts for the circuits, these are: Controllability:-the internal nodes within a chip are not reachable, i.e. designers do not have control over the inputs that can be provided to a particular module inside the chip under normal circumstances, Boundary SCAN helps in this regard by making the internal node input controllable. Observability:-Similar to the fact that the internal nodes are not controllable under normal circumstances, they are not observable as well i.e. their outputs are not visible to us (the internal module's output). This is where the Boundary SCAN Techniques help as it makes the internal module's output observable.
input/output register into boundary SCAN registers (very similar to the SCAN techniques, with just the contrast that it is scaled up from the chip level to the PCB level), hence each register will have an additional multiplexer, this multiplexer will either feed the D input of the register that is the normal input that is normally observed or a test input which is called the test data input. FIGURE-2: Schematic for I/O registers of Boundary SCAN As it is shown in Figure 2 each register has an additional multiplexer, the first register has a multiplexer that has two inputs that are, first the
normal input and another from an additional pin to the chip, this pin is called TDI (Test Data Input), the next pin for in figure 2 is an input pin which would normally accept input to the register in normal mode, whereas the other input of the multiplexer would be the output of the register that preceded this register, same would be done for all of the output and input pins so all registers are replaced by a SCAN register which has an extra multiplexer which always accepts the normal input and output of the preceding register as seen in figure 2. What this does is that it allows us to work in one of the two modes, and the mode will be set by the select lines of the multiplexer, so when it is in normal mode everything will be fed in parallel like that in figure 1, but if it is in test mode on the other hand then we will always pick the output of the preceding register as an input to the register, so the first register will accept TDI from the outside, the second register will accept the output of the first register, the third register will accept the output of the second register and so on. The final register will provide as an output to a pin called TDO (Test Data Output), there is another pin not shown in figure 2, called the test pin which runs to the
them has a TDI, TDO and a TEST pin (not shown in the figure), there will also be a TDI, TDO and TEST jack on the PCB itself to make it compatible with the boundary SCAN technique. Apart from the copper track shown in figure 3, there is another copper track that runs through the boundary of the PCB starting from the TDI jack of the PCB, what it is going to do is that it will go to the TDI pin of the first microchip and exit through the TDO pin of the first chip and similar will run through the next chip and one by one will run through every chip on the PCB and will finally exit through the TDO jack of the PCB, notice that this copper track will only be used in SCAN mode and also that this copper track should be made such that there are no crossovers of the copper track. The test pin is distributed to all of the test pins of all the microchips so that all the chips are in normal mode or the test mode simultaneously. When the PCB is in normal mode i.e. the test pin is 0 the copper track around the boundary is meaningless as the TDI and TDO pins of the chips are meaningless as the chips are operating in parallel mode similar to the registers case in figure 2, but when the test in is equal to 1, this assembly will work in test mode and hence will bypass the die core and will create a shift register from TDI to TDO as each microchip will create a boundary SCAN around its boundary, hence now there
is a complete loop from TDI to TDO and this loop contains a very long shift register which is formed of all the pins of all the chips, and this path is created using an independent copper track on the PCB. It is useful because when designers make PCB containing multiple chips, designers don't have the mechanical access to the pins, i.e. pins cannot be probed, but B-SCAN allows the designer to probe the values of the pins as they are part of a shift registers, not only that now the pins of any chip can be forced to a specific value. This can be understood with an example, suppose the designer wants to force the pins of chip 4 to a specific value, if the test is to be applied to chip 4 specifically what can be done is that the input pins of chip 4 is forced to a specific test vector value which can be done using the Boundary SCAN technique by setting the test mode to 1 and then shifting in the inputs until they are settled in the input pin registers of the chip 4 and then return to test mode equals 0 and apply enough clock cycles so that output can be taken from chip 4 and then the output can be shifted out of the output registers of chip 4. Another thing that the boundary SCAN technique can be used for and is used more often, is that it can be used the probe and ensure the integrity of the assembly i.e. the pins are connected to the copper tracks. If there is a problem
Boundary SCAN cell The Boundary SCAN cell is the basic building block of the Boundary SCAN technique, this is the cell that is used repeatedly to get the correct functionality, hence it is important to know this in detail. As shown in figure 4, the boundary SCAN cell consist of 2 multiplexers, the second multiplexer output represents the signal that is going to the die core, mode helps us to choose between the two modes, are the normal mode and the test mode, TDI is the test data in input and the TDO is the test data out, whenever the circuit is used in test mode inputs are given through the TDI pin and the output is taken from the TDO pin, which helps the boundary SCAN to work as one big shift register through which a particular probe can be given to a particular chip in the circuit. Other than the multiplexers there are two D flip flops there which would work as normal input/output registers in case of normal operation, but will work as a part of shift register if the operation mode is switched to test mode. The shift/load signal that is used as the select line of the first multiplexer works per the test input signal, as in, when the test signal is 0, the load signal will be active, corresponding to the normal
mode. When the test signal will be 1, the shift will be active which corresponds to the boundary SCAN working as one big shift register. Let us see the arrangement of these boundary SCAN register cells in our circuit terms. Figure 5, in-depth, describes the arrangement of the cells and how they can be used as normal I/O registers and shift registers if needed. FIGURE-5: Arrangement of the Boundary SCAN cells
