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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Module Title: Electronic Engineering
Module Code: ELXE E
School: Electrical & Electronic Engineering
Programme Title: Bachelor of Engineering Applied Electronics Design – Year 3
Programme Code: EAELN_7_Y EAELD_7_Y
External Examiner(s): Mr. David Denieffe, Dr. Paula O’Sullivan Internal Examiner (s): Mr. Patrick Collins
Instructions: Answer any four questions - 25 marks each. p=10-12^ , n=10-9^ , μ=10- m=10-3^ , k=10 3 , M=10 6
Duration: 2 Hours
Sitting: Winter 2007
Requirements for this examination: N/A
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you are attempting the correct examination paper. If in doubt please contact an Invigilator.
Q1. An op-amp has the following specifications:
At 25°C the input offset voltage is V (^) IO = 5mV, the input bias current is I (^) B = 100nA and the input offset current is I (^) IO = 9nA. ∆VIO /∆T = 15μV/°C, ∆I (^) B /∆T = 700pA/°C. A (^) OL=103.5dB. Unity Gain Bandwidth = 1.5MHz.
(a) Draw the frequency response of the magnitude of the open loop gain. Clearly identify the break frequency, the unity gain bandwidth and the slope of the roll-off. [ 4 marks ]
(b) The op-amp is configured as an inverting amplifier. The amplifier is required to have a closed loop bandwidth ( fCL ) of at least 40kHz. If the feedback resistor ( Rf ) = 56kΩ then work out the range of the other resistor ( R1 ). [ 7 marks ]
(c) If R1 = 5.6kΩ then what is the maximum possible output error voltage due to input offset voltage and input bias current effects at 25°C? If a balance resistor is used to reduce the output error voltage then what should this resistor value be and what will be the percentage reduction in the original error voltage? [ 7 marks ]
(d) If the temperature rises to 70°C then what is the new maximum possible output error voltage (with no balance resistor )? [ 7 marks ]
Q4.
R (^) D
VDD
R (^) G2 RS
R (^) G
FIGURE Q4a.
(a) For the circuit shown in Figure Q4a find I (^) D , VGS , V (^) DS and prove that the MOSFET is in saturation for the following conditions : VDD = 5V , RG1 = 47kΩ , RG2 = 39kΩ , RD = 1kΩ , RS = 470Ω , Vt = 0.5V , I (^) D = 100μA when V (^) GS = 0.7V. [ 15 marks ]
FIGURE Q4b.
(b) In Figure Q4b , V (^) t = 1V , k = 10μA/V^2 and M1 and M2 are identical. Find I (^) D2 if Vdd = 5V and R = 150kΩ. What is the min value of VDS2 for which this current flows? [ 10 marks ]
Q5. The layout used in this question is for a 2μm n-well CMOS scalable architecture. The grid spacing is 1λ = 1μm. The colour coding for the layers is shown below.
(a) A simple n-well CMOS process needs a minimum of seven layout layers. Name them and give a brief one-line description of the purpose of each one. How is the substrate handled in this system? [ 7 marks ]
(b) What is the difference between a drawn and a derived layer in a layout system? Use the creation of the gate oxide layer of a MOSFET as an example. [ 2 marks ]
(c) Explain DRC and LVS. Clearly outline the difference between them. [ 4 marks ]
(d) For the layout shown in Figure Q5 answer the following questions : (i) Identify each of the upper and lower transistors as an NMOS or PMOS device. Explain clearly how you came to this conclusion. (ii) What logic device is implemented in the circuit? (iii) What are the W and L dimensions for the upper and lower transistors? [ 6 marks ] (e) A process has a sheet resistance for polysilicon of 150 Ω/ and a minimum polysilicon dimension of 2μm. Its CAD system has a resolution of 0.1 μm. (i) If you require an overall resistance of 1kΩ then what is the minimum sized resistor you can layout with the closest possible value? (ii) If there is a +/- 0.1μm variation in the width then what is the variation in the final resistance? [ 6 marks ]
