MPC555 Bus Protocols and Interfacing: Understanding Bus Transactions and Arbitration, Slides of Microcontrollers

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Bus Protocols and Interfacing

• Bus basics
• I/O transactions
• MPC555 bus

Reference:

Chapter 9 of MPC555 User’s Manual

Basic example

• Discuss a basic bus protocol
  • Asynchronous (no clock)
  • Initiator and Target
  • REQ#, ACK#, Data[7:0], ADS[7:0], CMD
    • CMD=0 is read, CMD=1 is write.
    • REQ# low means initiator is requesting something.
    • ACK# low means target has done its job.

REQ# = REQ

Read transaction

ADS[7:0]

CMD

Data[7:0]

REQ#

ACK#

?? 0x24 ??

?? 0x55 ??

A B C D E F G HI

A write transaction

(write 0xF4 to location 0x31)

• Initiator sets ADS=0x31, CMD=1, Data=0xF
• Initiator then sets REQ# to low.
• Target sees write request.
• Target reads data from data bus. (Just has to store in a register, need not write all the way to memory!)
• Target then sets ACK# to low.
• Initiator sets REQ# to high & stops driving other lines.
• Target sets ACK# to high terminating the transaction

The LED

(1 bit reg written by LSB of address 0x05)

ADS[2]

ADS[0] ADS[1]

ADS[3] ADS[4] ADS[5] ADS[6] ADS[7] REQ#

Flip-flop which clock controls LED

D

DATA[2]

DATA[0] DATA[1]

DATA[3] DATA[4] DATA[5] DATA[6] DATA[7]

Delay ACK#

MPC555 Bus

The basic function of the MPC555 bus is similar, though slightly more complicated. (Chapter 9 of 555 User’s Manual)

• Timing is controlled by a global clock; all signals are in reference to the rising edge of this clock.
• 32-bit data bus D[0:31]
• 24-bit address bus A[8:31]
  • A[0:7] not sent off chip
  • On-chip peripherals still see 32 address bits
• Basic control lines:
  • RD/#WR
  • #TS (transfer start)—like #REQ but only asserted on first clock cycle of transaction
  • #TA (transfer acknowledge)—like #ACK

MPC555 Read(s)

CLK

A[8:31]

D[0:31]

RD/#WR

#TS

#TA

A

D

A

D

read @ A1 read @ A

MPC555 Write

• Same start as for a read, except for polarity of RD/WR#.
• Master drives data by 2nd^ cycle.
• Slaves look at address and RD/#WR when #TS is asserted. One of them will read data and assert #TA.
• As with reads, minimum transaction length is two cycles. Slaves can take longer, however, by not asserting #TA. Master keeps driving address, RD/#WR, and data until it sees #TA asserted.

• TSIZ[0:1] – Specifies the size of the data to be transferred. (aka “Port Size”)
• #Burst – Indicates a burst transaction
• #BDIP – Burst Data In Progress (more burst stuff)
• #BI – Burst Inhibit. Indicates that the slave doesn’t support burst transactions
• Many More…

Of course, things aren’t that simple

Example of complexity:

The Burst Mechanism (9.5.3)

• Burst transfers are used to move (up to) 16 bytes at a time
• #BURST must be asserted by master
• #BI must not be asserted by slave
• Must be a 16-byte aligned access
• Supports critical word first.

Arbitration (9.5.6)

Requesting device Arbiter

Request the bus

• Assert #BR

ACK bus mastership

• Wait for #BB to be deasserted
• Assert #BB
• Negate #BR

Perform data transfer

Release bus mastership

• Negate #BB

Grant bus arbitration

• Assert #BG

Terminate Arbitration

• Negate #BG

Transfer Alignment

0x

0 7 8 15 16 23 24 31

MPC555 external bus supports natural address alignment

• Byte access: Any address alignment
• Half-word access: Address bit 31 equal to 0
• Word access: Address bits 31 and 30 equal to 0