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A concise overview of key concepts in computer architecture, focusing on parallelism via instructions and multiple issue techniques. It defines terms such as static and dynamic multiple issue, issue slots, speculation, vliw, use latency, loop unrolling, antidependence, superscalar, dynamic pipeline scheduling, commit unit, reservation station, reorder buffer, out-of-order execution, and in-order commit. Each term is accompanied by a brief definition, making it a useful resource for understanding advanced pipelining and instruction execution methods. Structured as a series of definitions, making it easy to quickly grasp the fundamentals of parallel processing in computer architecture.
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Multiple Issue - correct answer ✔✔A scheme whereby multiple instructions are launched in one clock cycle. Static multiple issue - correct answer ✔✔An approach to implementing a multiple- issue processor where many decisions are made by the compiler before execution Dynamic multiple issue - correct answer ✔✔An approach to implementing a multiple issue processor where many decisions are made during execution by the processor. Issue slot - correct answer ✔✔The position from which instructions could issue in a given clock cycle Speculation - correct answer ✔✔An approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions Issue packet - correct answer ✔✔The set of instructions that issues together in one clock cycle; the packet may be determined statically by the compiler or dynamically by the processor. Very Long Instruction Word (VLIW) - correct answer ✔✔A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. Use latency - correct answer ✔✔Number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. Loop unrolling - correct answer ✔✔A technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together.
Antidependence - correct answer ✔✔Also called name dependence. An ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions. Superscalar - correct answer ✔✔An advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution. Dynamic Pipeline Scheduling - correct answer ✔✔Hardware support for reordering the order of instruction execution so as to avoid stalls. Commit Unit - correct answer ✔✔The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory. Reservation Station - correct answer ✔✔A buffer within a functional unit that holds the operands and the operation Reorder Buffer - correct answer ✔✔The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register. Out-of-order Execution - correct answer ✔✔A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait. In-order Commit - correct answer ✔✔A commit in which the results of pipelined execution are written to the programmer-visible state in the same order that instructions are fetched.