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C952 Computer Architecture PGKO Pre-Assessment
Practice Questions
1. Which access does a register file rely on to properly function? a) Read and write access b) Write only access c) Read only access d) No access: a 2. What is the binary representation of instructions? a) Machine language b) Assembly language c) Operating system d) Systems software: a 3. Which feature of the IBM 360/91 was incorporated into the majority of microprocessors developed in the 21st century? a) Branch prediction allowed the processor to proceed with the next instruc- tion. b) Algorithm innovations allowed the improved parallel execution of instruc- tions. c) Pipeline innovations allowed for reservation stations and the commit unit. d) Pipeline innovations allowed for dynamically scheduled pipelined proces- sors.: b 4. Which key design element changed in 2005 to drive continued improve- ments in computing capability? a) Multiprocessor architecture b) Transistor architecture c) DRAM technology d) Frame buffering: a 5. Which term refers to the same instruction applied to multiple data streams? a) SIMD b) MIMD
c) SPMD d) SISD: a
6. What makes vector-based code more efficient than conventional code? a) Usage of LEGv8 architecture code b) Usage of Multimedia extensions (MMX) c) Frequency of pipeline hazards is higher d) Frequency of pipeline hazards is lower: d 7. Which two elements are required to implement R-format arithmetic logic unit (ALU) operations? a) ALU and register file b) ALU and GPU c) GPU and register file d) Datapath and COD: a 8. Which component of a computer moderates the action of its other compo- nents? a) Control b) Datapath c) Memory d) Output: a 9. Given the following 8-bit integer binary variables: X1 = 11000110 X2 = 11110111 What is the value in X3 after the following command? ADD X3, X2, X a) Overflow b) 100111101 c) 11000110 d) 11110111: a 10. What is the approximate range of a 64-bit unsigned integer? a) 9,223,372,036,854,775,808 to 9,223,372,036,854,775, b) 2,147,483,648 to 2,147,483, c) 0 to 4,294,967, d) 0 to 18,446,744,073,709,551,615: d
c) Temporal d) Canonical: c
16. What does each bank of modern DRAMS consist of? a) Rows b) Disk c) Buffers d) Columns: a 17. What is meant by pipelining in computer architecture? a) It compensates for a serial portion of the program that would otherwise limit scalability. b) It employs an implementation technique where multiple instructions are overlapped in execution. c) It increases the size of the problem proportionally to the increase in the number of processors.: b 18. What is superscalar as it relates to parallelization? a) A buffer within a functional unit that holds the operands and the operation b) The hardware support for reordering the order of instruction execution so as to avoid stalls c) A process in which an instruction is blocked from executing, and therefore it fails to cause the following instructions to wait d) A technique that enables the processor to execute more than one instruc- tion per clock cycle by selecting them during execution: d 19. The value of b is stored in r1, c is stored in r2, and a is stored in r0. Which set of ARM instructions will accomplish a = b & c? a) AND r0, r1, r b) OR r0, r1, r c) EOR r0, r1, r d) ORR r0, r1, r2: a
20. Registers X1, X2, X3 have corresponding data stored in each location: X1: A X2: B X3: C Which set of ARM instructions will accomplish A=B+C? a) ADD X3, X2, X b) ADD X1, X2 #X c) ADD X3 #X2, X d) ADD X1, X2, X3: d 21. The variables f and g are assigned to the registers X3 and X4, respectively in these ARM instructions. Loop: SUBS XZR, X3, X B.GE Exit LSL X3, X3, 1 B Loop Exit: What are the corresponding statements in the C language? a) while (f < g) { f = f << 1; } b) while (f > g) { f = f << 1; } c) while (f <= g) { f = f << 1; } d) while(f == g){f = f << 1; }: a 22. Given this set of ARM instructions, where b is at offset 0, e is at offset 8, and a is at offset 24: LDUR X1, [X0,#0] LDUR X2, [X0,#8] ADD X3, X1, X STUR X3, [X0,#24]
c) a = b + a; d) a = e + a;: a
23. What is the number of bits used in virtual memory with ARMv8? a) 12 b) 16 c) 24 d) 48: d 24. Which register will be populated with the reason for an exception in LEGv8 architecture? a) ESR b) RAID c) FADDS d) FSUBS: a 25. Which statement about the operating system describes how virtual mem- ory is allocated in ARM architecture? a) It loads the page table register to refer to the page table of the process. b) It uses a reference bit to refer to the page table of the process. c) It loads the entire page table to reference the process. d) It uses a limit register to refer to the page table of the process.: a 26. What is used by virtual memory to increase performance? a) Translation-lookaside buffer b) Sparse memory c) Demand paging d) Page size: a 27. What maps virtual memory to real memory by using page tables? a) Each guest operating system manages virtual memory independently. b) The host operating system manages each virtual machine's virtual memory. c) The hypervisor software manages each virtual machine's virtual memory. d) Guest operating systems prohibit the use of virtual memory.: a 28. What are two benefits of using virtual machines? Choose 2 answers. a) Software abstraction
b) Hardware separation
How much faster would the instructions complete if executed 1, times using a pipelining methodology? a) 2 times b) 4 times c) 8 times d) 16 times: b
35. What is improved from all LEGv8 instructions having the same 32- bit length? a) Pipelining b) Caching c) Disk I/O d) Power consumption: a 36. What is the final value in X10 when the following code completes, given that X6 contains 20, X7 contains 10, and X8 contains 20? SUB X9, X7, X CBZ X6, AAA ADD X9, XZR, #1 B ZZZ AAA SUB X9, X8, X CBNZ X6, ZZZ ADD X9, XZR, #2 ZZZ ADD X10, XZR, X a) 0 b) 1 c) 2 d) 3: b 37. How can the CPU performance of a program be improved? a) By reducing the number of clock cycles b) By increasing the length of the clock cycle c) By reducing the throughput of the processor d) By increasing response time for disk access: a
38. A program runs alone on a CPU. The CPU clock rate is 3e9 cycles per second, i.e., 3 GHz. It takes the CPU 15e9 clock cycles to complete the program. The CPU clock cycle time is 500e-12 second, i.e., 500 picoseconds. How many seconds is the CPU performance for the task? a) 1. b) 7. c) 15 d) 75: b 39. A cache has 16 one-word blocks. Memory blocks are mapped to fully associative caches. Memory block is 15. What is the cache position given the cache configuration and memory block? a) Block 7 b) Block 15 c) Any of the 15 cache blocks d) Any of the 16 cache blocks: d 40. A program has a CPI of 10 on a target platform. The processor pipeline is expanded and clock rate is increased by a factor of 5, but the CPI fails to decrease accordingly. Which factor is negatively affecting performance? a) Cache memory b) Virtual memory c) Hard disk drive d) Single processor: a 41. Four processors (1, 2, 3, and 4) have clock frequencies of 200 Mhz, 300 Mhz, 500 Mhz, and 700 Mhz, respectively. Suppose:
- Processor 1 can execute an instruction with an average of 5 steps.
- Processor 2 can execute an instruction with an average of 3 steps.
- Processor 3 can execute an instruction with an average of 3 steps.
- Processor 4 can execute an instruction with an average of 5 steps. Which processor should be selected to improve performance for the
of the same instruction? a) Processor 1 b) Processor 2 c) Processor 3 d) Processor 4: c
42. Which technique should be implemented to reduce cache miss rate? a) Blocking b) Pipelining c) Parallel processing d) Loop unrolling: a 43. Which set-associative cache will improve overall performance? a) One-way b) Two-way c) Six-way d) Ten-way: b 44. A program requires one billion instructions to execute on a processor running at 4 GHz. Exactly 50% of the instructions execute in three clock cycles, 30% execute in four clock cycles, and 20% execute in five clock cycles resulting in an execution time of 1.075 seconds. Which adjustment improves overall performance by 12%? a) 30% execute at three cycles and 70% at four cycles b) 70% execute at three cycles and 30% at four cycles c) 100% execute at three cycles d) 100% execute at four cycles: b 45. Which instruction of the ARM architecture excludes a carry value after the arithmetic calculation? a) Reverse subtract b) Long multiplies c) No divide d) Conditional trap: a 46. Which three components or aspects specify the statement of a virtual machine?
a) Page table b) Program counter c) Registers d) Secondary storage cache e) Translation-lookaside buffer (TLB) f) System call
- Use commas between letters: "a, b, c, ...": a, b, c
47. A storage solution for video editing is being planned. The requirements are:
- Largest storage space
- No redundancy
- Fastest I/O speed Which RAID solution should be implemented? a) RAID 0 b) RAID 1 c) RAID 5 d) RAID 6: a 48. Which computer architecture idea is analogous to the assembly line? a) Dependability via parallelism b) Performance via pipelining c) Performance via prediction d) Dependability via redundancy: b 49. What is an advantage of using virtual memory technique? a) It increases the size of the primary memory available. b) It permits a program to exceed the size of primary memory. c) It shares a virtual address with the same physical address. d) It allows reading and writing to main memory in virtual machines.: b 50. What is an advantage of implementing cloud computing? a) It offers scheduled scaling. b) It provides automatic scaling. c) It provides local hosting by self-detection. d) It offers additional services by self-detection.: b
SUB M0, M0, R
B Loop Exit:: a
55. Which optimized processor architecture solves operations with large amounts of data-level parallelism? a) Vector b) SISD c) Scalar d) Uniprocessor: a 56. Which memory type is built as an integrated circuit that provides the fastest access but less density? a) Static random access memory (SRAM) b) Dynamic random access memory (DRAM) c) Graphics-based d) Cache: a 57. Which technology improves the efficiency of processor utilization by ensuring all processors remain utilized, even when waiting for instruction sequences to complete? a) Multithreading b) Multiprocessing c) Multicore processors d) Multiple processes: a 58. Why have recent CPU clock rates increased while power consumption has flattened out? a) Memory size requirements b) Chip sizes are too small c) Chip sizes are too large d) Cooling issues: d 59. A company needs the ability to host a low-cost network of servers and thin clients that host different operating systems needed to support differing applications. Which solution will meet these needs? a) RAID
b) Hypervisor c) RISC architecture d) Instruction-level parallelism: b
60. A system designer wants to lower the cost of communicating at a high clock rate over the network. How can this goal be accomplished? a) Increase the network latency b) Extend the length of the wires c) Reduce the distance of each link d) Implement a fully connected network: c
