Cache Memory - Computer Architecture - Lecture Slides, Slides of Computer Science

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Cache Memory

Revisiting Memory Hierarchy

• Facts

• Big is slow
• Fast is small

• Increase performance by having “hierarchy”

of memory subsystems

• “Temporal Locality” and “Spatial Locality”

are big ideas

Direct Mapped Cache

Direct Mapped Cache [contd…]

• What is the size of cache? 4K
• If I read 0000 0000 0000 0000 0000 0000 1000 0001
• What is the index number checked? 32
• If the number was found, what are the inputs to comparator?

Direct Mapped Cache [contd…]

• Advantage

• Simple
• Fast

• Disadvantage

• Mapping is fixed !!!

Associative Caches

• Block 12 placed in 8 block cache:
  • Fully associative, direct mapped, 2-way set associative
  • S.A. Mapping = Block Number Modulo Number Sets

Blockno. 0 1 2 3 4 5 6 7

Fully associative: block 12 can go anywhere Blockno. 0 1 2 3 4 5 6 7

Direct mapped: block 12 can go only into block 4 (12 mod 8) Blockno. 0 1 2 3 4 5 6 7

Set associative: block 12 can go anywhere in set 0 (12 mod 4)

Set 0

Set 1

Set 2

Set 3

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Block-frame address

Blockno. 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3

Example: 4-way set associative Cache

What is the cache size in this case?

Disadvantages of Set Associative Cache

• N-way Set Associative Cache versus Direct Mapped Cache:
  • N comparators vs. 1
  • Extra MUX delay for the data
  • Data comes AFTER Hit/Miss decision and set selection
• In a direct mapped cache, Cache Block is available BEFORE Hit/Miss:

Cache Data Cache Block 0

Cache Tag Valid

Cache Data Cache Block 0

Valid Cache Tag

Cache Index

Sel1 1 Mux^0 Sel

Cache Block

Adr Tag (^) Compare Compare

OR Hit

Cache Misses

• Compulsory (cold start or process migration, first reference): first access to a block - “Cold” fact of life: not a whole lot you can do about it - Note: If you are going to run “billions” of instruction, Compulsory Misses are insignificant
• Capacity:
  • Cache cannot contain all blocks access by the program
  • Solution: increase cache size
• Conflict (collision):
  • Multiple memory locations mapped to the same cache location
  • Solution 1: increase cache size
  • Solution 2: increase associativity
• Coherence (Invalidation): other process (e.g., I/O) updates memory

Design Options at Constant Cost

Direct Mapped N-way Set Associative Fully Associative

Compulsory Miss

Cache Size

Capacity Miss

Coherence Miss

Big Medium Small Same (^) Same Same

Conflict Miss High Medium Zero

Low Medium High Same Same Same

Where can a block be placed in the upper

level?

• Direct Mapped
• Set Associative
• Fully Associative

How is a block found if it is in the upper

level?

• Direct indexing (using index and block offset), tag compares, or combination
• Increasing associativity shrinks index, expands tag

Block offset

Block Address Tag Index

Set Select Data Select

What happens on a write?

• Write through —The information is written to both the block in the cache and to the block in the lower-level memory.
• Write back —The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. - is block clean or dirty?
• Pros and Cons of each?
  • WT: read misses cannot result in writes
  • WB: no writes of repeated writes
• WT always combined with write buffers so that don’t wait for lower level memory

Two types of Cache

• Instruction Cache

• Data Cache

IR

PC I -Cache

D Cache

A B

R

T

IRex

IRm

IRwb

miss

invalid

Miss