Spring 2004 Operating Systems Comprehensive Exam, Exams of Operating Systems

A comprehensive exam for an operating systems course, covering topics such as deadlock, virtual memory, and process scheduling. It includes questions about the banker's algorithm, translation lookaside buffer (tlb), page tables, and process scheduling algorithms.

Typology: Exams

2012/2013

Uploaded on 04/07/2013

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SPRING 2004 OPERATING SYSTEMS COMPREHENSIVE EXAM
You must answer ALL questions. Each solution should go in a separate blue book.
1. Consider a stream that has six stepping stones across it. To cross the stream, a
person puts one foot on the stone closest to her bank. Then, she puts her other foot
on the second stone in sequence. She proceeds walking across the stones in this
manner until she is on the other bank.
The stones are small - no more than one foot can be on a stone at a time.
a) Show that deadlock is possible in this system.
b) Give a simple condition that is true iff the system is deadlocked.
c) Consider using the Banker's algorithm to avoid deadlock. Give a simple
description of how the executions it allows avoid deadlock. In particular, describe
one execution in which there was no danger of deadlock but the Banker's algorithm
did not allow it to happen.
2. This problem is on Virtual Memory.
(a) Let's do some bit masking as warmup. Given a 17-bit virtual address space and
a page size of 128 bytes, what is the virtual page number of the virtual address
0x54FA? What is the offset?
A fundamental mechanism in modern virtual memory architectures is the
translation lookaside buffer (TLB).
(b) What does the TLB translate? What is the input and what is the output? What
does the TLB store as entries?
(c) When does a translation miss in the TLB, and, briefly, what needs to happen for
the TLB to resolve the miss?
(d) What is the difference between a hardware-managed TLB and a software-
managed TLB? What are the tradeoffs of one versus the other?
(e) Modern architectures with 64-bit virtual address spaces require new
innovations for page tables to represent and map such vast address spaces. Does
the TLB need to drastically change as well? What, if any, are the performance
implications of using a TLB with the same number of entries on a 32-bit architecture
versus a 64-bit architecture? Why? You can assume that applications on the 64-
bit architectures have orders of magnitude larger virtual address spaces than those
on the 32-bit architectures.
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SPRING 2004 OPERATING SYSTEMS COMPREHENSIVE EXAM

You must answer ALL questions. Each solution should go in a separate blue book.

  1. Consider a stream that has six stepping stones across it. To cross the stream, a person puts one foot on the stone closest to her bank. Then, she puts her other foot on the second stone in sequence. She proceeds walking across the stones in this manner until she is on the other bank. The stones are small - no more than one foot can be on a stone at a time. a) Show that deadlock is possible in this system. b) Give a simple condition that is true iff the system is deadlocked. c) Consider using the Banker's algorithm to avoid deadlock. Give a simple description of how the executions it allows avoid deadlock. In particular, describe one execution in which there was no danger of deadlock but the Banker's algorithm did not allow it to happen.
  2. This problem is on Virtual Memory. (a) Let's do some bit masking as warmup. Given a 17-bit virtual address space and a page size of 128 bytes, what is the virtual page number of the virtual address 0x54FA? What is the offset? A fundamental mechanism in modern virtual memory architectures is the translation lookaside buffer (TLB). (b) What does the TLB translate? What is the input and what is the output? What does the TLB store as entries? (c) When does a translation miss in the TLB, and, briefly, what needs to happen for the TLB to resolve the miss? (d) What is the difference between a hardware-managed TLB and a software- managed TLB? What are the tradeoffs of one versus the other? (e) Modern architectures with 64-bit virtual address spaces require new innovations for page tables to represent and map such vast address spaces. Does the TLB need to drastically change as well? What, if any, are the performance implications of using a TLB with the same number of entries on a 32-bit architecture versus a 64-bit architecture? Why? You can assume that applications on the 64- bit architectures have orders of magnitude larger virtual address spaces than those on the 32-bit architectures.
  1. At Wild Kingdom Park, visitors repeatedly wander the museum and then see the park by taking a ride in a car (one person per car). Assume there are M cars and N visitors, where M and N are integers greater than 0. A car must wait for a visitor before it begins riding around the park; if all cars are currently being used, then a visitor ready to take the ride must wait for a car to become free. Below is code that models the park as described above. Wait and Signal are semaphore operations. What, if anything, is wrong with this code: sem CA = 0; /* car available / sem VR = 0; / visitor ready to enter car / sem CR = 0; / car ready to start the ride / sem VD = 0; / visitor done with ride */ visitor () {
  2. wander_museum (); /* wander museum for random time */
  3. Wait (CA); /* wait for a car to become available */
  4. Signal (VR); /* visitor ready to enter car */
  5. Wait (CR); /* wait until car ready to go */
  6. Wait (VD); /* wait for ride to complete */ } car () {
  7. Signal (CA); /* this car is available */
  8. while (TRUE) {
  9. Wait (VR); /* wait until visitor is ready to enter */
  10. Signal (CR); /* car is ready to go */
  11. ride_park (); /* ride around park for some amount of time */
  12. Signal (VD); /* visitor done with ride */
  13. Signal (CA); /* car is now available again / } } main () { int i; for (i = 0; i < M; i++) { / start car processes / if (fork () == 0) { car (); } } for (i = 0; i < N; i++) { / start visitor processes */ if (fork () == 0) { visitor (); } } }