8086 Microprocessor Architecture: Segmentation, Features, and Bus Operation, Schemes and Mind Maps of Microprocessor and Assembly Language Programming

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ECEg-4701: Microcomputer and Interfacing

Chapter Two. The 8086

Microprocessor Architecture

Outline of the chapter

Features of 8086

Architecture of 8086 Register Organization Bus Operation

Memory Segmentation

6. The 8086 has multiplexed address and data bus which

reduces the number of pins needed, but does slow down the

transfer of data (drawback).

7. The 8086 requires one phase dock with a 33% duty cycle to

provide optimized internal timing.

8. It is possible to perform bit, byte, word and block operations

in 8086. It performs the arithmetic and logic operations on

bit, byte, word and decimal numbers including multiply and

divide.

Features of 8086

9. The Intel 8086 is designed to operate in two modes, namely the

minimum mode and the maximum mode. (min.=control signals are

issues by CPU, Max.=control signals are issued by external bus

controller (8288).

10. The Intel 8086 supports multiprogramming. In multiprogramming,

the code for two or more processes is in memory at the same time

and is executed in a time-multiplexed fashion.

11. Intel 8086 has 6 bytes instruction cache or queue.

12. The 8086 provides powerful instruction set with different addressing

modes such as Register, immediate, direct, indirect through an

index or base, indirect through the sum of a base and an index

register, relative and implied.

Features of 8086

• (^) Instruction queue:

The main linkage between the two functional blocks is the instruction

queue.

• (^) To speed up program execution, BIU fetches six instruction bytes ahead of time from the

memory and holds for the EU in a group of registers called Queue.

Queue makes possible to fetch next instruction when current instruction is in execution.

• (^) In case of JUMP and CALL instructions, instruction already fetched in queue are of no use.
• (^) Fetching the next instruction while the current instruction executes is called pipelining.

8

• (^) Execution Unit (EU)  (^) The EU of 8086 tells the BIU from where to fetch instructions or data, decodes instructions and executes instructions.  It contains:  (^) Control circuitry  (^) Instruction decoder  (^) ALU  (^) Register Organization  (^) Flag register  (^) General purpose register  (^) Pointers and Index registers
• (^) Control Circuitry, instruction Decoder, ALU:
• (^) The control circuitry in the EU directs the

internal operations.

• (^) A decoder in the EU translates the instructions

fetched from memory into a ,series of actions

which the EU performs.

• (^) ALU is 16-bit. It can add, subtract, AND, OR,

XOR increment, decrements, complement and

shift binary numbers.

 Register Organization  (^) General purpose registers:  (^) The 8086 has four 16-bit general purpose registers labeled AX, BX, CX and DX.  (^) They are used for holding data, variables and intermediate results temporarily.  (^) They can also be used as a counters or used for storing offset address for some particular addressing modes.  (^) AX is used as 16-bit accumulator whereas AL is used as 8-bit accumulator.  (^) BX is used as offset storage for generating physical addresses in case of certain addressing modes.  (^) CX is used as a default counter in case of string and loop instructions.

 Register Organization

 Segment Registers:

 (^) The physical address of the 8086 is 20-bit wide to access 1 Mbyte memory locations. However, its registers and memory locations which contain logical addresses are just 16-bits wide.  (^) 8086 uses memory segmentation. It treats the 1 Mbyte of· memory as divided into segments, with a maximum size of a segment as 64 Kbytes.

 The 8086 allows only four active segments at a time,

as shown in fig 2.5 and 16-bit segment registers are used for the selection.

 These four segment registers are: code segment (CS)

register, the data segment (DS) register, the stack segment (SS) register, and the extra segment (ES) register.

 Register Organization

 Pointers and Index Registers

 The registers in this group are all 16 bits wide and, unlike the data registers, cannot

be accessed as a low or high byte.

 These registers are used as memory pointers.

 Recall that all segment registers are 16-bit wide. But it is necessary to generate 20-

bit address (physical address) on the address bus.

 To get 20-bit physical address one or more pointer or index registers are associated

with each segment register.

 The pointer registers IP, and BP & SP are associated with code, and stack segments,

respectively.

 The index registers DI & SI are used as a general purpose registers as well as for

offset storage in some addressing modes.

14  Register Organization  (^) Flag Register

 A flag is a flip-flop which indicates some condition produced

by the execution of as instruction or controls certain operations

Of the EU.

 The flag register contains nine active flags as shown in the figure. Six of them

are used to indicate some condition produced by instruction.

1. CF: carry flag is set if there is a carry out of

the MSB or used as borrow flag for

subtraction (it is set when borrow is

needed)

2. PF: Parity flag is set if result of byte

operation or lower byte of the word

operation contain an even number of ones.

3. AF: Auxiliary flag is set if there is an

overflow out of bit 3 and is used for BCD

programmer.

4.ZF: Zero flag is set if result of ALU is zero.

And also if certain register content

becomes zero following an increment or

decrement operation.

5.SF: sign flag is set if MSB of the result is 1.

16  Register Organization  (^) Flag Register

The three remaining flags are used to control certain

operations of the processor.

1.TF: Trap flag is used for single stepping through a program (for debugging). If TF is set a trap is executed after execution of each instruction, i.e. interrupt service routine is executed which displays various registers and memory variable contents. 2.IF: Interrupt flag is used to allow/ prohibit the interruption of a program. If set, a certain type of interrupt (a maskable interrupt) can be recognized by the 8086; otherwise these interrupts are ignored. 3.DF: direction flag is used with string instruction. If DF = 0, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address.

 Bus Operation

Intel 8086 has a common address and data bus which are time multiplexed. The two bus is commonly known as multiplexed address and data bus. It provides the most efficient use of pins on the processor.

 (^) Memory Segmentation  (^) Note that for memory segmentation:

1. The 4 segments can overlap for small programs and can start at the address 00000H.
2. The segment can begins at any memory address which is divisible by 16.  (^) Advantages of memory segmentation
3. Allows the memory addressing capacity to be 1 Mbyte (though L.A is 16-bit)
4. Allows instruction code, data, and stack portion of program to be more than 64 KB long by using more than one code, data, stack segment, and extra segment.
5. Facilitates use of separate memory areas for program, data and stack.
6. Permits program relocation which is very useful in multiprogramming.

 (^) Memory Segmentation

 Generation of 20-bit address

 (^) The Intel 8086 generates 20-bit physical address using the contents of segment register and the offset register associated with it.  (^) offset registers include:  (^) Stack pointer: contains the 16-bit offset from the segment to the top of stack. E.g. if SS =4000H and SP=9F20H, then physical address= SS*10H+SP=40000H+9F20H=49F20H.  (^) Base pointer: can be used instead of SP in different addressing mode.  (^) Source Index: is used to hold the offset of a data word in the data segment.  (^) Destination Index: string instructions always use ES and DI to determine 20-bit physical address for the destination.