

Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
The specification of the cipher circuit, including its pseudocode, table of input/output ports, and timing requirements. The pseudocode outlines the logic of the circuit using variables a, b, c, d, u, t, and round keys s[j]. The table of input/output ports lists the width and meaning of each port, such as clk, reset, i, write_i, sj, write_sj, j, o, and done. The timing requirements assume 2r+4 clock cycles for loading round keys and r+2 clock cycles for encrypting a message block. Students may find this document useful for understanding the design of the cipher circuit, particularly for tasks related to drawing a block diagram of the datapath and interfacing the circuit with the controller.
Typology: Exercises
1 / 2
This page cannot be seen from the preview
Don't miss anything!


The CIPHER circuit is specified below using its:
Port Width Meaning clk 1 System clock. reset 1 System reset – clears internal registers. I 4 w Input block. write_I 1 Synchronous write control signal for the input block I. After the block I is written to the CIPHER unit, the encryption of I starts automatically. Sj w Round key S[j] loaded to one of the two internal memories. write_Sj 1 Synchronous write control signal for the round key S[j]. j m Index of the round key S[j] loaded using input Sj. O 4 w Output block. DONE 1 Asserted when the output O is ready. Note: m is a size of index j. It is a minimum integer, such that 2m^ - 1 ≥ 2r+3.
3. Timing Requirements: Assume that - 2r+4 clock cycles are used to load round keys to internal RAMs - r+2 clock cycles are used for encryption of a single message block of the size of 4w bits. Task 1 Draw a block diagram of the Datapath of the CIPHER circuit. Use medium complexity components corresponding to the operations used in the pseudocode. Clearly specify - names, widths and directions of all buses - names, widths and directions of all inputs and outputs of the logic components. Assume that one round of the main for-loop of the pseudocode executes in one clock cycle. Minimize the number of control signals to be generated by Control Unit. Mark the most likely critical path in your circuit. Task 2 Draw an interface of the CIPHER circuit with the division into Datapath and Controller.