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Circuit 4: Bridge Rectifier
A bridge rectifier circuit, shown below, provides full-wave rectification. Node numbers in the figure are indicated in blue, corresponding to the example SPICE description.
D
1 D 2
D (^3) D^4
load vIN
vOUT
Analysis:
Case 1: vIN > 0. In this case, we see that the most positive potential appears at the anode of D 2. Based on this, we may predict that D 2 is ON while D 1 is OFF. Since the most negative potential appears at the anode of D 4 , we may conclude that D 4 is OFF. Based on this reasoning, we infer that the current flows in a zig-zag through D 2 , then the load, then D 3. The potential appearing across the load is
vOUT ≈ vIN − 1 .4V.
Case 2: vIN < 0. In this case the most positive potential appears at the anode of D 4 , and the most negative potential appears at the cathode of D 1. We may conclude that the current flows in a zig-zag through D 4 , then the load, then D 1. In this case the potential appearing across the load is vOUT ≈ |vIN| − 1 .4V.
The bridge arrangement ensures that the polarity across the load is always oriented right-to-left, regardless of the input polarity.
· 10 −^2
Time
Voltage
Bridge Rectifier Circuit with 10V Input Amplitude
vin vout
Voltage Regulators
We previously considered a 0.7V regulator circuit. We can extend this concept to produce other regulated voltages by connecting multiple diodes in series. For example, we may connect four diodes in series to create a 2.8V regulator circuit: VDD
R
vOUT
Example: Regulator design
Let
vin = 10V + (0.5V) sin (2πf t).
Basic analysis
Find R to get an average current of 1mA, resulting in vout = 2.8V.
1mA = I =
vin − vout R ⇒ R =
vin − vout I = 7.2kΩ
The behavior of this circuit is investigated using SPICE simulation. The results shown below include a supply ripple with zero-to-peak amplitude of 0.5V at 120Hz.
· 10 −^2
Time
Voltage
Regulator Circuit with 120Hz Supply Ripple vin vout
Ripple Analysis: Line Regulation
The regulator is able to reject ripple waveforms that appear in the supply voltage, however the rejection is not perfect. A close inspection reveals that a small ripple is injected into vOUT:
· 10 −^2
Time
Voltage
Regulator Output Ripple
The regulator’s quality is measured by the amount of ripple that appears in vout. More precisely, we want to know the ratio of output ripple amplitude to input ripple amplitude. This quantity is called the line regulation, defined as
LR =
∆vOUT ∆VDD
To predict this, we must calculate the small-signal gain of AC signals that are transferred from vin to vout. We previously introduced a small-signal model that allows each diode to be replaced by a linear approximation. Now we introduce the concept of an AC Equivalent Circuit which we can use to analyze the non-DC behavior.
Deriving the AC Equivalent Circuit
Step 1 To obtain the linear circuit approximation, replace all non-linear devices (e.g. diodes) with their linearized companion models, as in previous examples.
Step 2 To obtain the AC equivalent circuit, set all independent DC sources to zero. This means that independent current sources are replaced by open-circuits, and independent voltage sources are replaced by short-circuits.
After obtaining the AC equivalent circuit, we use all-lower-case notation to indicate the ripple waveforms vin and vdd. Using the AC equivalent circuit, we can solve for the line regulation as the ratio of these small signals: LR ≈
vout vdd Reminder: The lower-case signal vout represents the small ripple signal appearing in the output. The all-upper-case notation VOUT is used to represent the DC (average) value. The actual physical signal is vOUT (t) = VOUT + vout (t).
VDD
R
rd
ID
VD^ −
rd
ID
VD^ −
rd
ID
VD^ −
rd
ID
VD^ −
vdd
R
rd
rd
rd
rd
vout
By using this model, we can obtain a reasonable estimate of vout, the small ripple waveform that is superimposed on the regulator’s output:
VDD
R
D 1
D 2
R 1
R 2
vOUT
For this configuration, the line regulation is:
LR = (G)
2 VT
(10V − 1 .4V) + 2VT
= 0.01202 (V/V).
So it appears that this solution is slightly better, although it may be affected by the tolerances on R 1 and R 2 , as well as the op amp’s input bias current and finite gain.
Super Diode, Precision Rectifier
vin^ + va
vout
Rload
This circuit operates in two modes. When the diode is forward biased, it is a unity-gain follower. Note that in this configuration vD can be very near zero, because little current is required to regulate the op amp’s inverting terminal. When the diode is reverse biased, the op amp is disconnected from the output node. Therefore it delivers no current to the load, and vout = 0. Note that in this configuration, the op amp’s loop is open, which will cause va to rail negative. Because of this issue, this circuit is best used with a single-sided power supply.
− 5 · 10 −^2 0 5 · 10 −^2 0.^1 0.^15 0.^2 0.^25 0.^3 0.^35 0.^4 0.^45 0.^5 0.^55
Time
Voltage
Superdiode With Single-Rail Supply
vin vout
∗ SPICE model f o r uA741 op amp ∗ ∗ To use a s u b c i r c u i t , the name must b e g i n with ’X ’. For example : ∗ X1 1 2 3 4 5 uA ∗ ∗ c o n n e c t i o n s : non−i n v e r t i n g i n p u t ∗ | i n v e r t i n g i n p u t ∗ | | p o s i t i v e power s u p p l y ∗ | | | n e g a t i v e power s u p p l y ∗ | | | | output ∗ | | | | |
. s ub c kt uA741 1 2 3 4 5 ∗ c1 11 12 8. 6 6 1E− 12 c2 6 7 3 0. 0 0E− 12 dc 5 53 dx de 54 5 dx dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 p o l y ( 2 ) ( 3 , 0 ) ( 4 , 0 ) 0. 5. 5 f b 7 99 p o l y ( 5 ) vb vc ve v l p v l n 0 1 0. 6 1 E6 −10E6 10E6 10E6 −10E ga 6 0 11 12 1 8 8. 5E− 6 gcm 0 6 10 99 5. 9 6 1E− 9 i e e 10 4 dc 1 5. 1 6E− 6 hlim 90 0 vlim 1K q1 11 2 13 qx q2 12 1 14 qx r2 6 9 1 0 0. 0 E r c 1 3 11 5. 3 0 5 E r c 2 3 12 5. 3 0 5 E r e 1 13 10 1. 8 3 6 E r e 2 14 10 1. 8 3 6 E r e e 10 99 1 3. 1 9 E ro1 8 5 50 ro2 7 99 100 rp 3 4 1 8. 1 6 E vb 9 0 dc 0 vc 3 53 dc 1 ve 54 4 dc 1 vlim 7 8 dc 0 v l p 91 0 dc 40 v l n 0 92 dc 40 . model dx D( I s =800.0E− 18 Rs=1) . model qx NPN( I s =800.0E− 18 Bf =93.75) . ends
DC Restoration, Clamped Capacitor
vin
C
vout
In this circuit the behavior depends on the capacitor’s charge q.
vout = vin +
q C When the diode is forward biased, the capacitor is able to be charged via current flowing through the diode. When the diode is reverse biased, no current flows, so that capacitor holds its charge. To analyze the circuit, consider the initial condition q (t = 0) = 0, so that initially vout = vin. Suppose vin is initially zero, and increases above zero. Then the diode will stay reverse biased, and q doesn’t change. But if vin decreases below zero, then the diode will begin to switch on. The capacitor will accumulate charge equal to
q (t) = iDt
= IS exp
−vout VT
t.
This current will be greater than zero as long as vout < 0. Consequently, the capacitor will collect charge until vout = 0. As a result of this process, the capacitor will store a voltage equal to the minimum value of vin. Result: vout is a shifted version of vin, such that its minimum value is equal to zero.
∗ DC r e s t o r a t i o n c i r c u i t
∗ G e n e r i c d i o d e model :
. model d i o d e d ( I s =2.0298 e −15 , n=1)
∗ The i n p u t i s a 10Hz s i n e wave : Vin 1 0 SIN (0 1 10)
∗ Peak d e t e c t o r c i r c u i t : D1 0 2 d i o d e C1 1 2 10uF
∗ T r a n s i e n t s i m u l a t i o n :
. t r a n 1m 2 . end
