Clock Synchronization - Digital System Design - Lecture Slides, Slides of Digital Systems Design

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Clock Synchronization

 Timing Issues

 Compare the following implementations …

 Both attempt to “enable” the change in the D flip-flop

 Is one preferred over the other?

 Yes – the AND gate version is simpler but undesirable

D Q

Q

Data Clock E

D Q

Q

Q

R

Clock

E

 Clock Distribution Network

 To ensure that all wires to flip-flops are of the same

length, and that the skew (if any) is the same …

 Use an H-tree distribution network

Clock ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Docsity.com

 Global Clock / Reset

 PLDs use a common global clock wired to all flip-

flops

 No gates used to slow the clock signal

 Global reset is also commonly provided

 More Timing Parameters

 Output from the flip-flop changes after a register

delay of trd

 Output from the flip-flop will appear on the output

pin of the chip after an output delay time of t

od D Q Data Clock Chip package pin A B t (^) Clock t (^) Data Out t (^) od

combinational logic

trd

 Clock to Output Timing

 A typical “clock to output” change t

co

is given by

 tco = tClock + trd + tod = 1.5 ns + 1 ns + 2 ns = 4.5 ns

 This is the time between an active edge of the Clock on the

input pin of the chip to the time at which the output is

observed on the output pin of the chip

 Flip-Flop Timing in a Chip (2)

 Need larger setup time from the viewpoint of the

input pins

 Need 6 ns gap between change in Data and active clock

edge at the input pins

Data Clock A 6ns 4.5ns 1.5ns B 3ns

setup time met

 Asynchronous Inputs

 What do you do when the inputs to a circuit arrive

asynchronously with respect to the clock?

 Maybe they are generated off the chip

 Worry about violating the setup/hold times

 If the setup/hold times are violated, the output of the FF

may assume a voltage level that is neither 0 nor 1

  Enters a metastable state

 Eventually enters 0 or 1, but can’t predict which nor when

 Synchronizing Asynchronous Inputs (1)

 Use a data synchronizer to catch an asynchronous

input and synchronize it when it first enters the

system

 Never allow asynch inputs to fan out to more than one FF

in a system

data synchronizer

May become metastable,

but will recover as long as

CCT is long enough

Very unlikely to ever

become metastable

Synchronous

output

 Synchronizing Asynchronous Inputs (2)

 Use this circuit when the input pulses will be > 1

clock period wide

 The extra flip-flop guards against metastability

 Case 1: the data synchronizer FF goes metastable

and eventually falls back to 0

Asynchronous input has been synchronized

 Synchronizing Asynchronous Inputs (4)

 Use this circuit when the input pulses will be < 1

clock period wide

Guards against metastability

Allows for long pulses as well as short ones

Note: multiple short pulses occurring within

a single clock period will be missed

 Debouncing Asynchronous Inputs

 Asynchronous inputs may also require “smoothing”

to eliminate any glitches in the input due to

mechanical “bouncing” of the signal

 A pushbutton input usually suffers from this problem

 Need to detect the pushbutton input, but ignore the

bounced signal

 Also note that pushbuttons are active low, so it is

convenient to invert the input signal to be active high

 Main idea: as soon as an input of 0 is detected, output a 1

 Only revert to 0 again after about 40 ms of continuous

unasserted input

 Trimming the Input Signal

 Debounced inputs may also be asserted for >> 1

clock cycle due to external requirements

 Pushbutton may be manually held down for many cycles

 It may be desired to “trim” a multi-cycle input to a single

cycle pulse

 Assume the input is already debounced (for simplicity)

A/0 B/

C/

 Verilog for One Pulse Signals