CMOS Logic Implementation: Pull-ups, Pull-downs, and Gates, Assignments of Very large scale integration (VLSI)

CMOS Logic Implementation

• Pull-up - A network that provides a low resistance path to Vdd

when

input is logic ‘0' and provides a high resistance to Vdd when input is

logic ‘1'.

• Pull down - A network that provides a low resistance path to

Gnd

when input is logic ‘1' and provides a high resistance to Gnd when

input is logic ‘0'.