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EE215 Computer Organization & Architecture
Spring 2017
Assignment – 1
Question - 1 A microprocessor is connected to 8 multiplexed bus lines. A partial list of registers for this processor is given below:
- PC (Program Counter), IR (Instruction Register), MAR (Memory address register), MBR (Memory buffer register) are the special purpose registers.
- R1 & R2 are the general purpose registers. Following set of instructions is executed for the given microprocessor. TABLE 1: Instruction Address Instruction Machine Code (hex)
Comments 1 F123 Mov R1, 3B00 hex 10A 01 3B00 Move contents of memory location 3B to register R 2 F124 Mov R2, 3B02 hex 10A 02 3B02 Move contents of memory location 3B to register R 3 F125 ADD R1,3B02hex 10B 01 3B02 Add the contents of memory location 3B02 to contents of register R1 and store the result in R1. 4 F126 SUB R2, 3B01hex 10C 02 3B01 Subtract the contents of memory location 3B01 from the contents of register R and store the result in R2. 5 F127 STORE 3B03hex, R1 10D 3B03 01 Store the contents of register R1 at the memory location 3B03.
TABLE2: Memory location Contents (hex) 3B00 02 3B01 05 3B02 08 3B03 01 3B04 06
Question - 3 A computer has a two-level cache. Suppose that 60% of the memory references hit on the first level cache, 35% hit on the second level, and 5% miss. The access times are 5 nsec, 15 nsec, and 60 nsec, respectively, where the times for the level 2 cache and memory start counting at the moment it is known that they are needed (e.g., a level 2 cache access does not even start until the level 1 cache miss occurs). What is the average access time? = 0.6 x 5n + 0.35x (5n + 15n) + 0.05 x (5n + 15n + 60n) = 14 ns
Question – 4 Consider a computer with the following characteristics: total of 1Mbyte of mainmemory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. Main Memory = 1M = 2^20 1 Block = 16 bytes/words = 2^4 (as 1word=1byte here) Number of blocks in main memory = 1M / 16 = 2^16 Cache = 64K = 2^16 bytes , number of cache lines = 2 16 / 2^4 = 2 12 A. For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache.
Bits 0-3 indicate the word offset (4 bits)
Bits 4-15 indicate the cache slot (12 bits)
Bits 16-19 indicate the tag (remaining bits)
F0010 = 1111 0000 0000 0001 0000
Word offset = 0000 = 0
line#= 0000 0000 0001 = 001
Tag = 1111 = F
Word offset = 0100 = 4
line# = 0001 0010 0011 = 123
Tag = 0000 = 0
CABBE = 1100 1010 1011 1011 1110
Word offset = 1110 = E
line# = 1010 1011 1011 = ABB
Tag = 1100 = C
B. Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache.3FFF0, 2FFF C. For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache.
For fully associative cache: tag bits = s = 16bits F0010: Word offset = 0h, Tag = F001h CABBE Word offset = Eh Tag = CABBh D. For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache. K = 2, no. of sets in a cache= 2^12 / 2 = Bits 0-3 indicate the word offset, Bits 4-14 indicate the cache set, Bits 15-20 indicate the tag F0010 = 1111 0000 0000 0001 0000 Word offset = 0000 = 0, Cache Set = 000 0000 0001 = 001, Tag = 11110 = 1 1110 = 1E CABBE = 1100 1010 1011 1011 1110 Word offset = 1110 = E, Cache Set = 010 1011 1011 = 2BB, Tag = 11001 = 1 1001 = 19
Question - 5 Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss.Where in the cache is the word from memory location ABCDE8F8 mapped?
Cache size = 16KB = 2^14 bytes, 1 line = 4 x 4 bytes = 16 bytes, number of lines = 2 14 / 16 = 2^10 K=4, number of sets= 2^10 /4 = 2 8 W=4, r = 8, ABCDE8F8 = > r=8F, w= 8
