1. Write very brief and to-the-point answers.
a. Why loading idtr with a value appropriate for real mode is
necessary while gdtr is not?
b. What should we do in protected mode so that when we turn
protection off, we are in unreal mode?
c. If the line jmp code:next is replaced with call code:somefun,
the prefetch queue is still emptied. What problem will occur
when somefun will return?
d. How much is ESP decremented when an interrupt arrives.
This depends on weather we are in 16-bit mode or 32-bit.
Does it depend on any other thing as well? If yes, what?
e. Give two instructions that change the TR register.
2. Name the following descriptors like code descriptor, data descriptor,
interrupt gate etc.
gdt: dd 0x00000000, 0x00000000
dd 0x00000000, 0x00000000
dd 0x80000fA0, 0x0000820b
dd 0x0000ffff, 0x00409a00
dd 0x80000000, 0x0001d20b
3. Using the above GDT, which of the following values, when moved into
DS will cause an exception and why.
0x00
0x08
0x10
0x18
0x28
0x23
4. Using the above GDT, if DS contains 0x20, which of the following
offsets will cause an exception on read access?
0x0ffff
0x10000
0x10001
5. The following function is written in 32-bit code for a 16-bit stack.
Against every instruction, write the prefixes generated before that
instruction. Prefixes can be address size, operand size, repeat, or
segment override. Then rewrite the code such that no prefixes are
generated considering that this is assembled and executed in 32-bit
mode. Don’t care for retaining register values. The function copies
specified number of DWORDs between two segments.
7. Protected mode has specialized mechanism for multitasking using task state
segments but the method used in real mode i.e. saving all registers in a PCB,
selecting the next PCB and loading all registers from there is still applicable.
Multitask two tasks in protected mode multitasking without TSS. Assume that
all processes are at level zero so no protection issues arise. Be careful to
save the complete state of the process.
8. Write the following descriptors.
a. 32 bit, conforming, execute-only code segment at level 2, with base
at 6MB and a size of 4MB.
b. 16 bit, non-conforming, readable code segment at level 0, with base
at 1MB and a size of 10 bytes.
c. Read only data segment at level 3, with base at 0 and size of 1MB.
d. Interrupt Gate with selector 180h and offset 11223344h.
11. Give short answers.
a. How can a GPF (General protection fault) occur while running
the following code
push es
pop es