Combinational circuits_Digital Electronics, Summaries of Electrical and Electronics Engineering

Combinational circuits_Digital Electronics

Typology: Summaries

2025/2026

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Combinational Arithmetic

Circuits

 Addition:

 Half Adder (HA).

 Full Adder (FA).

 Binary Adder

 BCD(Decimal) Adder.

 Subtraction:

 Half Subtractor.

 Full Subtractor.

 Multiplication:

 Binary Multipliers.

 Comparator:

 Magnitude Comparator.

Half Subtractor

Half Subtractor Truth Table

 Subtracting a single-bit binary value Y from anther X (I.e. X

-Y ) produces a difference bit D and a borrow out bit B-out.

 This operation is called half subtraction and the circuit to

realize it is called a half subtractor.

D(X,Y) =  (1,2)
D = X’Y + XY’
D = X  Y

Inputs Outputs

B-out(x, y, C-in) =  (1)
B-out = X’Y

X Y D B-out 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 X Y

Half
Subtractor

D B-OUT X Y Difference D

B-out

Binary Arithmetic Operations

Subtraction

 Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed.  Subtraction Example: 00 00 11 11 11 11 11 00 00 BorrowBorrow X 229 1 1 1 0 0 1 0 1 Y - 46 - 0 0 1 0 1 1 1 0 183 1 0 1 1 0 1 1 1

Full Subtractor Circuit Using

AND-OR

Y Y Y’ X X X’ B-in B-in B-in’ X’Y’B-in XY’B-in’ X’YB-in’ (^) Difference D X’ X X’ Y’ Y B-in Y B-in’ B-in’ X X’Y YB-in X’ X’B-in B-out X’ Y B-in Y B-in B-in (^) B-in’ XYB-in X Y B-in’

Full
Subtractor

X Y D B-out B-in

Full Subtractor Circuit Using XOR

Difference D X Y B-in

Full X’ X’Y

X Y B-out X’Y YB-in X’ X’B-in B-out X’ Y B-in Y B-in

Full
Subtractor

D B-out B-in

Binary Subtractor

  • The subtrcation A – B can be done by taking the 2’s complement of B and adding it to A because A- B = A + (-B)
  • It means if we use the inveters to make 1’s complement of B (connecting each Bi to an
  • It means if we use the inveters to make 1’s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.

4 bit 2’s complement Subtractor

Checking Overflow

  • Note that in the previous slide if the numbers considered to be signed V detects overflow. V= means no overflow and V=1 means the result is wrong because of overflow
  • Overflow can be happened when adding two numbers of the same sign (both negative or positive) Overflow can be happened when adding two numbers of the same sign (both negative or positive) and result can not be shown with the available bits. It can be detected by observing the carry into sign bit and carry out of sign bit position. If these two carries are not equal an overflow occurred. That is why these two carries are applied to exclusive-OR gate to generate V.
K-map for P

Design example: 2x2-bit

multiplier (cont’d)

B A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 B B A 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

B2 P8 = A2A1B2B
K-map for P
P4 = A2B2B1'
+ A2A1'B
K-map for P

A B A 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 A B A 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 A B A B

P2 = A2'A1B
+ A1B2B1'
+ A2B2'B
+ A2A1'B
K-map for P
P1 = A1B

Assignment-

  • Explain half Subtractor and Full Subtractor.