Download Combinational logic circuits - Digital Systems - Exam and more Exams Digital Systems Design in PDF only on Docsity!
CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Autumn Examinations 2010/
Module Title: Digital Systems 2
Module Code: ELTR
School: Electrical and Electronic Engineering
Programme Title: Bachelor of Engineering in Electronic Engineering
Programme Code: EELES_8_Y EELXE_7_Y
External Examiner(s): Dr A Donnellan Mr I Kennedy
Internal Examiner(s): Mr J O’Sullivan
Instructions: Attempt any three questions. All questions carry equal marks. Ensure to include the Return Sheet with your answer book.
Duration: Two hours
Sitting: Autumn 2011
Requirements for this examination: N/A
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
You are expected to present your material in a neat and clear fashion. Start each question on a new page. Remember that you have plenty of time for this exam – two hours for three questions.
Q1 (a) Using diagrams of simple switch circuits, briefly explain what is meant by the combinational logic circuits known as multiplexers and demultiplexers. [4 marks]
(b) One of the circuits above is known as a data distributor, the other as a data selector. With reference to your diagrams in (a), state which is which giving a reason in each case for your conclusion. [2 marks]
(c) Draw a logic symbol and truth table for a 4-line version of one of the circuits above, either a multiplexer or a demultiplexer, and use the truth table to derive a Boolean equation for any outputs shown. [6 marks]
(d) Using the equations, draw a full logic diagram for the circuit in (c) above. [5 marks]
(e) Figure 1 below is a pinout diagram of the 74LS151 chip. Identify this chip and briefly explain the function controlled by the signal applied to pin 7, ( EN ). [3 marks]
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
D0 Y Y EN
A0 S D2 D
D4 D5 D6 D7 S0 S
Vcc
Gnd
Figure 1
Q2 (a) Shift registers can be used for serial-to-parallel and parallel-to-serial data conversion. Using block diagrams, explain fully what is meant by the above statement. [6 marks]
(b) Draw a full circuit diagram of a 4-bit shift register capable of converting data from parallel to serial format and explain briefly how data is entered into this circuit. [8 marks]
(c) Figure 2 below is a functional block diagram of the 74LS165 shift register chip. Show how a number of these could be wired up to implement a circuit capable of carrying out 16-bit parallel-to-serial data conversion. [6 marks] D
SH/LD
D1 D2 D
SER (^) SRG- 74LS
D4 D5 D6 D
CLK CLK INH
Q
CLK Q
Figure 2
Q4 (a) Figure 4 below shows the diagram of a simple flip-flop circuit. What logic level would appear on the output of this circuit as it is drawn? – explain your conclusion. What overall function does this circuit perform? [3 marks]
(b) Describe the action of the circuit when the switch in the circuit changes down – draw a timing diagram to show the output signal when this occurs. [4 marks]
(c) Draw a logic symbol and full truth table for a negative edge-triggered J-K flip-flop complete with asynchronous preset and clear inputs. [5 marks]
(d) Attached to this paper is an extract from the data sheet for the 74LS112 J-K flip- flop chip, © Motorola. Study this sheet and answer the following questions: (i) what is the maximum clock frequency that can be applied? (ii) explain what is meant by tPLH and state a typical value for this parameter (iii) for the normal 16-pin plastic version of this chip that we used in the lab, (N suffix), what is the distance in millimetres between adjacent pins? [4 marks]
(e) On the Return Sheet accompanying this paper is a J-K flip-flop circuit and an associated timing diagram. Carefully examine the circuit and complete the timing diagram, assuming the signal sequence shown is applied to the flip-flop. When complete, write down the relationship between the CLK signal and the output signal in the box provided. [4 marks]
+5V
O/P
Figure 4
CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Autumn Examinations 2010/
Module Title: Digital Systems 2
Return Sheet
J (^) Q
K
T CLK
O/P
T
O/P
CLK
Relationship between CLK and O/P signals:
Name: Return this sheet with your answer book
