Logic Technologies: Programmable Devices, MOS Transistors, Multiplexers/Decoders, and ROM, Slides of Digital Systems Design

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Lecture 4

Combinational Logic Implementation

Technologies

Outline

• Review of Combinational Logic Technologies

• Programmable Logic Devices (PLA, PAL)

• MOS Transistor Logic

• Multiplexers/Decoders

• ROM

• READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4,

PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of AND gates Product terms

Dense array of OR gates

Outputs

Why PALs/PLAs Work

Example:

F0 = A + B' C'

F1 = A C' + A B

F2 = B' C' + A B

F3 = B' C + A

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term 0 = negated in term

- = does not participate

1 = term connected to output 0 = no connection to output

Input Side:

Output Side:

Product Inputs Outputs term

Reuse of terms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0

F 1

F 2

F 3

A B

B C

A C

B C

A

Example of PALs and PLAs (Contd)

Unwanted connections are "blown"

Note: some array structures work by making connections rather than breaking them

Alternative Representations

Short-hand notation so we don't have to draw all the wires!

Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

Differences Between PALs and PLAs

PAL concept — implemented by Monolithic Memories constrained topology of the OR Array

A given column of the OR array has access to only a subset of the possible product terms

PLA concept — generalized topologies in AND and OR planes

Design Example: BCD-to-Gray Code

Converter

Truth Table (^) K-maps

W = A + B D + B C

X = B C'

Y = B + C

Z = A'B'C'D + B C D + A D' + B' C D'

Minimized Functions:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X AB CD 00 01 11 10 00 01 11 10

D

B

C

A

0 0 X 1 0 1 X 1 0 1 X X 0 1 X X

K-map for W

AB CD 00 01 11 10 00 01 11 10

D

B

C

A

0 1 X 0 0 1 X 0 0 0 X X 0 0 X X

K-map for X

AB CD 00 01 11 10 00 01 11 10

D

B

C

A

0 1 X 0 0 1 X 0 1 1 X X 1 1 X X

K-map for Y

AB CD 00 01 11 10 00 01 11 10

D

B

C

A

0 0 X 1 1 0 X 0 0 1 X X 1 0 X X

K-map for Z

Non-Gate Logic

AND-OR-Invert PAL/PLA

Generalized Building Blocks Beyond Simple Gates

So far we have seen:

Kinds of "Non-gate logic":

**- switching circuits built from CMOS transmission gates

• multiplexer/selecter functions
• decoders
• tri-state and open collector gates
• read-only memories**

Steering Logic: Switches

Voltage Controlled Switches

Gate Oxide Source Drain Silicon Bulk

Channel Region

Metal Gate, Oxide, Silicon Sandwich

Diffusion regions: negatively charged ions driven into Si surface

Si Bulk: positively charged ions

By "pulling" electrons to the surface, a conducting channel is formed

"n-Channel MOS"

n-type Si p-type Si

Logic Gates with Steering Logic

Logic Gates from Switches

+5V

A (^) A

+5V

A (^) B

A B

+5V

A (^) B

A + B

Inverter NAND Gate^ NOR Gate

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors

Inverter with Steering Logic

Inverter Operation

+5V

"1" (^) "0"

+5V

"0" (^) "1"

Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND

Input is 0 Pull-up conducts Pull-down does not conduct Output connected to VDD

NOR Gate with Steering Logic

NOR Gate Operation

+5V

"0" (^) "0"

"1"

+5V

"1" (^) "0"

"0"

A = 0, B = 0

Pull-up network conducts Pull-down network broken Output node at VDD

A = 1, B = 0

Pull-up network broken Pull-down network conducts Output node at GND

CMOS Transmission Gate

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

In Out

Control

Control

In Out

Control

Control

In (^) Out

Control

Control

Switches (^) Transistors Transmission or "Butterfly" Gate