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Material Type: Notes; Professor: Bosworth; Class: Computer Architecture; Subject: Computer Science; University: Columbus State University; Term: Unknown 2009;
Typology: Study notes
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Basically, sequential circuits have memory and combinational circuits do not. Here is a basic depiction of a sequential circuit. All sequential circuits contain combinational logic in addition to the memory elements. We now consider the analysis and design of sequential circuits.
In this course, we represent sequential circuits as finite state machines. A Finite State Machine (FSM) is a circuit that can exist in a finite number of states, usually a rather small number. Finite State Machines with more than 32 states are rare. The FSM has a memory that stores its state. If the FSM has N states, then its memory can be implemented with P flip–flops where 2 P– < N 2 P Typical values: 3 states 2 flip–flops 4 states 2 flip–flops 5 states 3 flip–flops 8 states 3 flip–flops Tools to describe finite states machines include
Here is the state diagram for a modulo–4 counter. There is no input but the clock. It just counts clock pulses. Note the direction of the arrows; this is an up–counter.
Transition tables are just state tables in which the labels have been replaced by binary numbers. Often the labels are retained to facilitate translation to binary. Here is the transition table for the sequence detector. Present State Next State / Output X = 0 X = 1 A = 000 000 / 0 001 / 0 B = 001 000 / 0 010 / 0 C = 010 011 / 0 010 / 0 D = 011 000 / 0 100 / 0 E = 100 000 / 0 010 / 1 Here is the transition table for the modulo–4 counter. There is no output table. Present State Next State 0 = 0 0 0 1 1 = 0 1 1 0 2 = 1 0 1 1 3 = 1 1 0 0
The analysis of such a circuit follows a fixed set of steps.
Input: X Output: Z = X Y Input to Flip–Flop: D = X +Y Output of Flip–Flop: Y
Here is the next state table.
We know the present state of the flip–flop; call it Y. Given Y and X, the input, we can compute D. This determines the next state. Here is the output table. It depends on the input and present state.
Here again is the state table with output. Present State Next State/Output X = 0 X = 1 0 0 / 0 1 / 1 1 1 / 1 1 / 0 Here is the state diagram. This is the required answer.
This is often hard to do. The key here is that the circuit stays in state 0 until the first 1 is input. When the first 1 is input it goes to state 1 and stays there for all input. We now characterize the output as a function of the input for each of the two states. Input Q(T) Output
It can be shown that this is a serial generator for a two’s–complement. The binary integer is read from Least Significant Bit to Most Significant Bit. Up to and including the first (least significant) 1, the input is copied. After that it is complemented. 0001 1100 becomes 1110 0100 0010 1101 becomes 1101 0011. Try this, it works.
Step 1: Derive the state diagram and state table for the circuit. Here is the state diagram. Note that it is quite simple and involves no input. Here is the state table for the modulo–4 counter Present State Next State 0 1 1 2 2 3 3 0
Obviously, there are only four states, numbered 0 through 3. Determine the number of flip–flops needed. Solve 2 P– < N 2 P
. If N = 4, we have P = 2 and 2 1 < 4 2 2 . We need two flip–flops for this design. Number them 1 and 0. Their states will be Q 1 and Q 0 or Y 1 and Y 0 , depending on the context. Remember: 2 1 = 2, 2 2 = 4, 2 3 = 8, 2 4 = 16, 2 5 = 32, 2 6 = 64, 2 7 = 128, etc.
Present State Next State 0 00 01 1 01 10 2 10 11 3 11 00 Strictly speaking, we should have dropped the decimal labels in this step. However, this representation is often useful for giving the binary numbers. The state transition table tells us what the required next state will be for each present state.
Here P = 2, so we need two tables. Flip-Flop 1 Flip-Flop 0 Present State Next State Present State Next State Y 1 Y (^0) Y
Each flip–flop is represented with the complete present state and its own next state.
