Components and Design Techniques for Digital System - Assignment 10 | COMPSCI 150 | Assignments Computer Science

Page 1

University of California, Berkeley

College of Engineering

Computer Science Division

Electrical Engineering and Computer Science Department

Computer Science 150 R. H. Katz

Fall 2000

Problem Set #10/11 (Assigned 16 November, Due 1 December)

1. Introduction

Your task is to complete the high level design of a very simple 4-bit computer. This will involve designing

the datapath and a control state machine to the state diagram level to implement the instruction set. This is

a very good example of the kind of comprehensive question you can expect to find on the final examina-

tion.

The machine has a single accumulator (R0), a single bit carry register (C), four general purpose registers

(R0, R1, R2, R3), four accumulator oriented instructions (COMP, INC, CLC, ADC), three register-register

instructions (ADD, AND, XFER), two register-memory instructions (LOAD, STOR), and a conditional

branch instruction (BRN). These instructions are encoded in from one to three 4-bit instruction parcels.

The machine can address 256 x 4-bit words.

2. Instruction Set

Instructions are encoded in from one to three 4-bit words. Arithmetic instructions are encoded in a single

word: two opcode bits (X3X2) and two operand bits (X1X0). All arithmetic instructions use R0 as an accu-

mulator. The C register receives the carry-out of all 4-bit additions. The operand bits specify one of the four

on-chip registers. The COMP, INC, CLC and ADC instructions involve the Accumulator and Carry regis-

ters only, and use the operand bits to encode the four different operations.

Arithmetic Instructions

Op Code (Binary) Op Code (Symbolic) Function

00 X1X0ADD C, R[0] ← R[0] + R[X1X0]

01 X1X0AND R[0] ← R[0] AND R[X1X0]

10 00 COMP R[0] ← ~R[0]

10 01 INC C, R[0] ← R[0] + 1

10 10 CLC C ← 0

10 11 ADC C, R[0] ← R[0] + C

An opcode of 11 represents an extended instruction, and the remaining two bits of the word specify one of

the four remaining instructions. An instruction word of 1100 encodes a register transfer instruction. The

operands are encoded in the following word: the high order two bits identify the destination register, while

the low order two bits identify the source.

Op Code (Binary) Op Code (Symbolic) Function

1100 Y3Y2Y1Y0 XFER R[Y3Y2]

← R[Y1Y0]

The remaining three instructions are encoded in three 4-bit words: 1 word for the extended op code, and

two words to identify the target address (memory extends from location 0 through location 25510).

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University of California, Berkeley College of Engineering Computer Science Division Electrical Engineering and Computer Science Department

Computer Science 150 R. H. Katz Fall 2000

Problem Set #10/11 (Assigned 16 November, Due 1 December)

1. Introduction

Your task is to complete the high level design of a very simple 4-bit computer. This will involve designing

the datapath and a control state machine to the state diagram level to implement the instruction set. This is

a very good example of the kind of comprehensive question you can expect to find on the final examina-

tion.

The machine has a single accumulator (R 0 ), a single bit carry register (C), four general purpose registers

(R 0 , R 1 , R 2 , R 3 ), four accumulator oriented instructions (COMP, INC, CLC, ADC), three register-register

instructions (ADD, AND, XFER), two register-memory instructions (LOAD, STOR), and a conditional

branch instruction (BRN). These instructions are encoded in from one to three 4-bit instruction parcels.

The machine can address 256 x 4-bit words.

2. Instruction Set

Instructions are encoded in from one to three 4-bit words. Arithmetic instructions are encoded in a single

word: two opcode bits (X 3 X 2 ) and two operand bits (X 1 X 0 ). All arithmetic instructions use R 0 as an accu-

mulator. The C register receives the carry-out of all 4-bit additions. The operand bits specify one of the four

on-chip registers. The COMP, INC, CLC and ADC instructions involve the Accumulator and Carry regis-

ters only, and use the operand bits to encode the four different operations.

Arithmetic Instructions

Op Code (Binary) Op Code (Symbolic) Function

00 X 1 X 0 ADD C, R[0] ← R[0] + R[X 1 X 0 ]

01 X 1 X 0 AND R[0] ← R[0] AND R[X 1 X 0 ]

10 00 COMP R[0] ← ~R[0]

10 01 INC C, R[0] ← R[0] + 1

10 10 CLC C ← 0

10 11 ADC C, R[0] ← R[0] + C

An opcode of 11 represents an extended instruction, and the remaining two bits of the word specify one of

the four remaining instructions. An instruction word of 1100 encodes a register transfer instruction. The

operands are encoded in the following word: the high order two bits identify the destination register, while

the low order two bits identify the source.

Register Transfer Instruction

Op Code (Binary) Op Code (Symbolic) Function

1100 Y 3 Y 2 Y 1 Y 0 XFER R[Y 3 Y 2 ] ← R[Y 1 Y 0 ]

The remaining three instructions are encoded in three 4-bit words: 1 word for the extended op code, and

two words to identify the target address (memory extends from location 0 through location 255

Memory Reference Instructions

Op Code (Binary) Op Code (Symbolic) Function

1101 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 LOAD R[0] ← MEM[Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 ]

1110 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 STOR MEM[Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 ] ← R[0]

1111 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 BRN IF R[0]<3>=

THEN PC ← Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0

3. Memory Interface

The processor has the following input/output connections to the outside world: RESET (on reset, the PC is

set to ZERO), clock, bidirectional data lines D 3 D 2 D 1 D 0 , and address lines A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0. The

interface to memory is exactly as in Laboratory #5: the processor generates a CS (chip select) and WE

(write enable) signal to control RAM directly. We make the significant simplifying assumption that the

processor clock period will exceed the RAM access time (i.e., the memory is a 0-Wait State Memory). See

Figure 1.

The processor should be implemented with a program ROM and a data RAM. Instructions are always

fetched from the ROM.

To load/examine program data, the processor should also include a simple “operator’s console” of status

LEDs and input switches. It will include a GO push button and a READ/WRITE switch to load or examine

the contents of RAM, along with a switch input to place the processor in a RUN/EXAMINE mode. When

in RUN mode, the processor executes the normal instruction fetch/decode/execute cycles. The operator’s

console in inactive, and its memory interface signals are left unasserted. When placed in the EXAMINE

mode, the processor completes the execution of the current instruction and enters an idle state, in which the

address and data lines are tri-stated, and the memory interface signals are unasserted (driven high). The

operator’s console is now active. Eight external switch inputs determine the address of a memory location

to be read and output to LEDs or written from four data switches. The READ/WRITE switch determines

the direction of access. The GO button commences a RAM read or write cycle, including appropriate con-

trol for the latches and buffers of the console’s datapath.

4. Sample Programs

The Carry Clear (CLC) and Add with Carry (ADC) instructions make it possible to implement additions of

CPU

Program

ROM Data RAM

Addr Bus

Data Bus

255

4 4

Switch

CS Instr

CS Data

Components and Design Techniques for Digital System - Assignment 10 | COMPSCI 150, Assignments of Computer Science

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Download Components and Design Techniques for Digital System - Assignment 10 | COMPSCI 150 and more Assignments Computer Science in PDF only on Docsity!

Problem Set #10/11 (Assigned 16 November, Due 1 December)

1. Introduction

Your task is to complete the high level design of a very simple 4-bit computer. This will involve designing

the datapath and a control state machine to the state diagram level to implement the instruction set. This is

a very good example of the kind of comprehensive question you can expect to find on the final examina-

tion.

The machine has a single accumulator (R 0 ), a single bit carry register (C), four general purpose registers

(R 0 , R 1 , R 2 , R 3 ), four accumulator oriented instructions (COMP, INC, CLC, ADC), three register-register

instructions (ADD, AND, XFER), two register-memory instructions (LOAD, STOR), and a conditional

branch instruction (BRN). These instructions are encoded in from one to three 4-bit instruction parcels.

The machine can address 256 x 4-bit words.

2. Instruction Set

Instructions are encoded in from one to three 4-bit words. Arithmetic instructions are encoded in a single

word: two opcode bits (X 3 X 2 ) and two operand bits (X 1 X 0 ). All arithmetic instructions use R 0 as an accu-

mulator. The C register receives the carry-out of all 4-bit additions. The operand bits specify one of the four

on-chip registers. The COMP, INC, CLC and ADC instructions involve the Accumulator and Carry regis-

ters only, and use the operand bits to encode the four different operations.

Arithmetic Instructions

Op Code (Binary) Op Code (Symbolic) Function

00 X 1 X 0 ADD C, R[0] ← R[0] + R[X 1 X 0 ]

01 X 1 X 0 AND R[0] ← R[0] AND R[X 1 X 0 ]

10 00 COMP R[0] ← ~R[0]

10 01 INC C, R[0] ← R[0] + 1

10 10 CLC C ← 0

10 11 ADC C, R[0] ← R[0] + C

An opcode of 11 represents an extended instruction, and the remaining two bits of the word specify one of

the four remaining instructions. An instruction word of 1100 encodes a register transfer instruction. The

operands are encoded in the following word: the high order two bits identify the destination register, while

the low order two bits identify the source.

Register Transfer Instruction

Op Code (Binary) Op Code (Symbolic) Function

1100 Y 3 Y 2 Y 1 Y 0 XFER R[Y 3 Y 2 ] ← R[Y 1 Y 0 ]

The remaining three instructions are encoded in three 4-bit words: 1 word for the extended op code, and

two words to identify the target address (memory extends from location 0 through location 255

Memory Reference Instructions

Op Code (Binary) Op Code (Symbolic) Function

1101 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 LOAD R[0] ← MEM[Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 ]

1110 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 STOR MEM[Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 ] ← R[0]

1111 Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0 BRN IF R[0]<3>=

THEN PC ← Y 3 Y 2 Y 1 Y 0 Z 3 Z 2 Z 1 Z 0

3. Memory Interface

The processor has the following input/output connections to the outside world: RESET (on reset, the PC is

set to ZERO), clock, bidirectional data lines D 3 D 2 D 1 D 0 , and address lines A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0. The

interface to memory is exactly as in Laboratory #5: the processor generates a CS (chip select) and WE

(write enable) signal to control RAM directly. We make the significant simplifying assumption that the

processor clock period will exceed the RAM access time (i.e., the memory is a 0-Wait State Memory). See

Figure 1.

The processor should be implemented with a program ROM and a data RAM. Instructions are always

fetched from the ROM.

To load/examine program data, the processor should also include a simple “operator’s console” of status

LEDs and input switches. It will include a GO push button and a READ/WRITE switch to load or examine

the contents of RAM, along with a switch input to place the processor in a RUN/EXAMINE mode. When

in RUN mode, the processor executes the normal instruction fetch/decode/execute cycles. The operator’s

console in inactive, and its memory interface signals are left unasserted. When placed in the EXAMINE

mode, the processor completes the execution of the current instruction and enters an idle state, in which the

address and data lines are tri-stated, and the memory interface signals are unasserted (driven high). The

operator’s console is now active. Eight external switch inputs determine the address of a memory location

to be read and output to LEDs or written from four data switches. The READ/WRITE switch determines

the direction of access. The GO button commences a RAM read or write cycle, including appropriate con-

trol for the latches and buffers of the console’s datapath.

4. Sample Programs

The Carry Clear (CLC) and Add with Carry (ADC) instructions make it possible to implement additions of

CPU

Program

ROM Data RAM

Addr Bus

Data Bus

Figure 1: CPU/Memory Interface