ECS154A, Section 2
Final Lab Project
Date Distributed: 11-09-00
Date Due: 12-11-00
You will design part of a clock distributor in this project. Now, what is a clock distributor? Simply put, it
has only one inputs with fundamental frequency, and generates multiple clock outputs with various
frequencies. It also has some other control inputs (which generally come from some other chip in a
computer) which controls the outputs.
Now that what we know are trying to do in this project, let’s have some more details how this part of the
design works.
Assumption: You have only two clock inputs in your design – one (CLKIN1) with a frequency of 100
MHz, and the other (CLKIN2) with 200 MHz. You have five (mandatory) special control signal inputs as
described later. You can use any number of other control signals – however, you need to keep this number
as small as possible.
Goal: You have the following outputs from your design- one clock output (CLKOUT1) of either 100 or
200 MHz, two clock outputs (CLKOUT2 and CLKOUT3) of 50 MHz, and five clock outputs (CLKOUT4-
7) of 25 MHz. Now there are some special timing relations between these clocks:
1. CLKOUT1 and CLKOUT2-3 are in phase – meaning that when CLKOUT1 has a rising edge,
CLKOUT2-3 will also have a rising edge.
2. CLKOUT1 leads CLKOUT4 by 1 ns – meaning that each rising edge of CLKOUT4 comes 1 ns after
each rising edge of CLKOUT1.
3. CLKOUT4 leads CLKOUT5-7 by 2.5 ns – meaning that each rising edge of CLKOUT4 occurs 2.5ns
before the rising edge of CLKOUT5-7.
Control Signals: You have the following control signals which affect the outputs in following manner-
1. In_Sel – selects the CLKOUT1 to be either 100 or 200 MHz.
2. STOP1 – The outputs CLKOUT2-3 are stoppable by this signal after their next transition.
3. STOP2-3 – Only one of the outputs CLKOUT5-7 are stoppable by these signals after two transitions.
However when both these signals are asserted, all of these four outputs will resume normal operation.
4. PWRDWN – When asserted, each clock output will be forced to LOW (0) after three transitions. When
deasserted, each clock will resume normal operation after 10 ns.
Your presentation of the project: Show your work (please type this up) – start with a block diagram of
your design, an ASM for your design, a target timing diagram of your design (hand-drawn) as per
ASM/block diagram, and justify all these parts. Now build the circuit using MAXPLUS II, and then
synthesize it. Check if your synthesis results and your hand-drawn timing diagram match. Show your
analysis in detail.
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