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Digital Logic Design

Version 4.8 printed on April 2018

First published on August 2006

Background and Acknowledgements This material has been developed for the first course in Digital Logic Design. The content is derived from the author’s educational, technical and management experiences, in-addition to teaching experience. Many other sources, including the following specific sources, have also informed by the content and format of the following material:  Katz, R. Contemporary Logic Design. (2005) Pearson.  Wakerly, I. Digital Design. (2006) Prentice Hall.  Sandige, R. Digital Design Essentials. (2002) Prentice Hall.  Nilsson, J. Electrical Circuits. (2004) Pearson. I would like to give special thanks to my students and colleagues for their valued contributions in making this material a more effective learning tool. I invite the reader to forward any corrections, additional topics, examples and problems to me for future Thanks,

Izad Khormaee

www.EngrCS.com © 2014 Izad Khormaee, All Rights Reserved.

• Chapter 1. Number Systems, Number Representations, and Codes
  • 1.1. Key concepts and Overview
  • 1.2. Digital vs. Analog
  • 1.3. Digital Design Overview (from Transistor to Super Computer)
  • 1.4. Design Methodologies
  • 1.5. Number Systems (Decimal, Binary, Octal, Hexadecimal)
  • 1.6. Base Conversions
  • 1.7. Signed Binary Number Conventions
  • 1.8. Binary Arithmetic
  • 1.9. Binary Codes
  • 1.10. DC Electrical Circuit Fundamentals
  • 1.11. Additional Resources
  • 1.12. Problems
• Chapter 2. Boolean Algebra, Functions, and Minimization
  • 2.1. Key concepts and Overview
  • 2.2. Logic Gates
  • 2.3. Huntington’s First Set of Postulates
  • 2.4. Principle of Duality
  • 2.5. Boolean Functions
  • 2.6. Boolean Algebra Theorems
  • 2.7. Canonical or Standard Form of Functions
  • 2.8. Methods of Function Minimization (reducing the number of literals in an expression)
  • 2.9. Karnaugh-map or K-map
  • 2.10. Special Case: “Don’t Care” Terms
  • 2.11. XOR Properties and Applications
  • 2.12. Additional Resources
  • 2.13. Problems
• Chapter 3. Analyzing and Synthesizing Combinational Logic Circuits
  • 3.1. Key concepts and Overview
  • 3.2. Standard Logic and Schematic Layout (Review)
  • 3.3. Designing Logic Circuits
  • 3.4. Combinational Logic Analysis and Design
  • 3.5. Compressing Truth Tables and K-maps
  • 3.6. Glitches and Their Causes
  • 3.7. Types of Functions and Delays
  • 3.8. Beyond Standard Logic: Applications
  • 3.9. Programmable Logic Devices (PLDs)
  • 3.10. Additional Resources
  • 3.11. Problems
• Chapter 4. Introduction to Feedback Circuits and Sequential Logic Analysis
  • 4.1. Key concepts and Overview
  • 4.2. SR Flip-Flops
  • 4.3. Asynchronous Sequential Logic Issues
  • 4.4. Finite State machine
  • 4.5. Additional Flip Flops
  • 4.6. Sequential Circuit Analysis
  • 4.7. Debouncing Mechanical Switches
  • 4.8. Additional Resources
  • 4.9. Problems
• Chapter 5. Sequential Circuit Design & Techniques
  • 5.1. Key concepts and Overview
  • 5.2. Synchronous Finite State Machine Design (Classical Design)
  • 5.3. State Assignment Encoding, Shift Register Counters, and Adding an Enable Input
  • 5.4. Inspection Design Methods for Finite State Machines
  • 5.6. FSM Design Examples
  • 5.7. Additional Resources
  • 5.8. Problems
• Chapter 6. Finite State Machine Optimization & Testing
  • 6.1. Key concepts and Overview
  • 6.2. State Minimization and FSM Design Process
  • 6.3. State Minimization Using an Implication Chart (or Table)
  • 6.4. Design for Testability (DFT)
  • 6.5. Additional Resources
  • 6.6. Problems
• Chapter 7 “Verilog”. Verilog Hardware Description Language (Verilog)
  • 7.1. Key concepts and Overview
  • 7.2. History
  • 7.3. Introduction to Verilog HDL...........................................................................................................
  • 7.4. Syntax
  • 7.5. Blocks and Assignments...............................................................................................................
  • 7.6. Operators
  • 7.7. Types and Variable Declarations
  • 7.8. Flow Control Statements
  • 7.9. Code Modularization
  • 7.10. Summary.....................................................................................................................................
  • 7.11. Additional Resources
  • 7.12. Problems
• Chapter 8 “VHDL”. VHDL Hardware Description Language (VHDL)
  • 8.1. Key concepts and Overview
  • 8.2. History
  • 8.3. Steps in VHDL design...................................................................................................................
  • 8.4. Entity and Architecture..................................................................................................................
  • 8.5. Declarations
  • 8.6. Operators
  • 8.7. Behavioral Design
  • 8.8. Dataflow Design Elements............................................................................................................
  • 8.9. Additional Resources
  • 8.10. Problems
• Chapter 9. Commercial Digital Integrated Circuits and Interface Design
  • 9.1. Key concepts and Overview
  • 9.2. Output Types
  • 9.3. Logic Families
  • 9.4. Multiplexer (MUX)/DeMultiplexer (DMUX) Design
  • 9.5. Adder & Subtractor Design
  • 9.6. Multiplier Design
  • 9.7. Arithmetic Logic Unit (ALU) Design
  • 9.8. Additional Resources
  • 9.9. Problems
• Appendix A. Additional Resources

1.2. Digital vs. Analog

Natural forces and signals are all analog (or continuous) which means we hear, see and change items in a continuous manner. On the other hand, our digital technology (also called non-continuous or 2-value discrete) more effectively allows us to process and communicate more effectively. This leads us to design systems that fit the following block diagram architecture:  Why convert analog data to digital data?  We have the information we need (on-off, timing)  Above a certain level is on, high, 1-state or true.  Below a certain level is off, low, 0-state or False. Note: We have introduced a discontinuity when a signal goes from 1 to 0 or 0 to 1. This means we cannot say what the exact value is at the time of transition.  Reduces complexity of signals and the solutions to work with the signal.  To deal with a digital signal we need to deal with binary algebra.  To deal with an analog signal we need to deal with calculus to approximate.  Positive vs. Negative logic  Positive Logic Convention (Default  easier for humans to understand)  H, (V > Vmax) is 1-state or True  L, (V < Vmin) is 0-state or False  Negative Logic Convention (1 is L and 0 is H)  H, (V > Vmax) is 0-state or False  L, (V < Vmin) is 1-state or True Real World Signal Analog to Digital Convertor (Audio, ..) Process/ Store/ Communicate Convertor Digital to Analog Convertor (Audio, ..) Real World Signal Example: Music Microphone Memory Chip Speaker Music

 Example of analog and digital representations of human Heart Beat:  Based on the definition of a digital (2-valued) system, what are some examples where a digital system could apply? What are the variables and on/off or high/low states?  Example: Describe the input and output of a traffic intersection in digital form. Solution: Car’s presence at an intersection: (Car PresentMagnitude is 1, No Car PresentMagnitude is 0) Status of Traffic Lights: (Red-on  1, Red-off  0) Extension: draw a typical Intersection and label the output and input in digital form. t

V

Vmax Vmin H (>Vmax) L (<Vmin)

V

t Analog to Digital Converter (ADC) Digital to Analog Converter (DAC)

Digital

Analog

 Medium Scale Integration, MSI  PAL--Programmable Array Logic, GAL--Generic Array Logic, EPROM--Erasable Programmable Read Only Memory, ADDER, COUNTER)  1,000s to 100,000s of gates.  Typically, the vendor provides information in the form of a data sheet  Large Scale Integration (LSI)  100,000s to Millions of gates  Typically implements complex functionality  Processors such as special function controllers and interface chips  Very Large Scale Integration (VLSI)  Millions to Billions of gates  Typically includes extensive functionality  Processors such as Intel’s Pentium are examples of VLSI.  Design / Analysis tools  We will be using manual processes for most of this text to design/analyze digital circuits in order to gain in-depth understanding of logic design.  The final section of this text is dedicated to the use of Hardware Description Language (HDL) to automate design, simulation, implementation, and analysis and verification process.

1. Block Diagram

A B

Input Output A B 0 1

2. Truth Table A B (^) t Propagation Delay
3. Timing Diagram

A

B

4. Equivalent Circuit

+5 V

GND

1.4. Design Methodologies

Digital design depends on the type of problem, the work already completed, the strategic direction of the organization and the skills/resources available to the project team. Having said that, in general, there are three approaches available to the designers under traditional Hierarchical-Oriented Designs:  Top-down Design Methodology Start with larger block of design and then work out the detail of each block.  Bottom-up Design Methodology Start with components and figure out how to interconnect them to design the system.  Middle-out Design Methodology A combination of the bottom-up and top-down. Most designs are done this way: start with the top-down design, then modify the design to take advantage of the available components (based on cost, availability, and reliability). Another way of thinking about the problem of design that has a strong following in the software development community and is being used in the hardware community under the module design concept is Object-Oriented Design (OOD). Designers commonly agree that there are four main properties or benefits associated with object-oriented design:  Encapsulation As the name implies, the internals of the design are hidden from the user and only the interface definition (input/output) are available to the user. Users benefit since they have a limited amount of information to learn. Designers benefit since they are able to upgrade the module without involving the user as long as the new interface is a superset of an existing interface.  Inheritance This simply means that an object may be built on the features available in the base object property. Of course, the benefit is that the designers only have to work on the additional feature and simply reuse the existing functionality.  Polymorphism OOD allows the designer to create objects that behave differently based on the attributes of input.  Composition (One object can be built using many others.) A new object may be developed based on the composition of multiple existing objects. Hopefully, at this point you are thinking “why wouldn’t everyone use OOD?” The main drawback of OOD is the high level of planning required for each module, and discipline needed to follow the four properties in design.

Note: The general term for decimal point is radix point  In binary, the count starts at 0 (called 0-referencing), where in decimal, the count typically starts with 1 (called 1-referencing)  Octal (base 8) and Hexadecimal (base 16) These number systems are used by humans as a representation of long strings of bits since they are:  Easier to read and write, for example (347) 8 is easier to read and write than (011100111) 2.  Easy to convert (Groups of 3 or 4)  Today, the most common way is to use Hex to write the binary equivalent; two hexadecimal digits make a Byte (groups of 8-bit), which are basic blocks of data in Computers.  Question: The hexadecimal system is base 16, so the digits range in value from 0 to 15. How do you represent Hexadecimal digits above 9? Use A for 10, B for 11, C for 12, D for 13, E for 14 and F for 15. So (CAB) 16 or (CAB)HEX is a valid hexadecimal number.  Computer memory is typically organized in 8-bit groups or bytes. Why groups of 8?

1.6. Base Conversions

 Decimal to Binary Conversion  Alternative 1 – “Subtract the weight method”

 Steps:

 Find the largest power of 2 (2n) that can be subtracted out of the decimal number  Take the result and subtract (2n-1) from it  If the result is not negative then that bit is one  If the result is negative, then that bit is zero and the result equals the result from step 1  Repeat step 2 until the result is exactly 0

 Example: convert (49) 10 to a binary number

 Alternative 2 – “Division by 2 method”

 Steps:

 Divide the decimal number by 2  Remainder is the least significant bit (most right bit)  Quotient is used in the next step  Divide quotient by 2  Remainder is the next significant bit (next left bit)  Quotient is used in the next step  Repeat previous step until quotient is 0

 Example: convert (49) 10 to a binary number

 Binary to Decimal Conversion – “Add the weight method”  Step: Simply multiply each bit with its weight and add to get the decimal number  Example: Convert (110001) 2 to a decimal number (110001) 2 = ( 1* 2^5 + 1* 2^4 + 0* 2^3 + 0* 2^2 + 0* 2^1 + 1* 2^0 ) 10 = (49) 10  Binary  Octal Conversion - “Group of 3 method” Remainder 2|49 1 (LSB) 2|24 0 2|12 0 2| 6 0 2| 3 1 2| 1 1 (MSB) 2| 0 Stop

2 n^  Results 

Binary #  ( 1 1 0 0 0 1) 2

0 When =0, done

 Example: Convert (52) 10 to binary (radix, r = 2)

Therefore (52) 10 = (110100) 2  Decimal Fraction Conversion to any Base – “Repeated Radix Multiplication Method”  Solution is based on the approach: (decimal fraction) 10 = d-1 r--1^ + d-2 r--2^ + … = (.dn…d 2 d 1 d 0 )r r*(decimal fraction) 10 = d-1 + d-2r-1^ + … = (.d-1d-2d-3 … )r  Steps: (1) Multiply (fraction) 10 by r, the non-fractional part is the first digit (2) Continue step 2 until fraction is 0  Example: Convert (.125) 10 to binary (r=2) Solution: Therefore (.125) 10 = (.001) 2 Note: Some numbers may not be fully convertible, so you have to decide the number of decimal points you need to convert. For example (1/12) 10 does not fully convert to binary number.

x 2

d-

x 2

d-

x 2

d- Fraction is 0 which means d-3 is the Least Significant Digit Non-fraction portion is 1 which means d-3 is 1. Non-fraction portion is 0 which means d-1 ,the Most Significant Digit, is 0.

Remainders R 0 =d 0 =0 R 1 =d 1 =0 R 2 =d 2 =1 R 3 =d 3 =0 R 4 =d 4 =1 R 5 =d 5 =

Quotient is 0 therefore remainder is MSB First Remainder is the LSB

1.7. Signed Binary Number Conventions

 Signed Binary Number Representations (3 methods)  Signed Magnitude (SM)  Easiest for people to read (Not used by computers)  Here is an example of Signed Magnitude number with 4-bit word size  Binary SM numbers for n-bit word ranges from +(2n-1^ – 1) to -(2n-1^ – 1) Note: there are two values for zero (Sign-bit = 1 and Sign-bit=0)  Example of complete list of binary SM numbers for a 4-bit word. Binary SM Number (n=4) Decimal Number d3 d2 d1 d 0 1 1 1 + 7 = +(24 -1^ -1) 0 1 1 0 + 6 0 1 0 1 + 5 0 1 0 0 + 4 0 0 1 1 + 3 0 0 1 0 + 2 0 0 0 1 + 1 0 0 0 0 + 0 1 0 0 0 - 0 1 0 0 1 - 1 1 0 1 0 - 2 1 0 1 1 - 3 1 1 0 0 - 4 1 1 0 1 - 5 1 1 1 0 - 6 1 1 1 1 - 7 = -(24 -1^ -1)  Diminished Radix Complement (DRC) or 1’s complement  Some computer systems use this information because it is easier to convert.  To obtain a negative DRC or 1’s complement:  Write a positive number with MSB set to 0 (positive sign)  Negate (Invert) every bit including sign bit to obtain the negative number.

(+5) 10 = (0 1 0 1 )2SM

( -5) 10 = (1 1 0 1)2SM

One Sign Bit 0  + 1  - 3 Magnitude Bit

 RC numbers for n-bit word range from +(2n-1^ – 1) to –(2n-1) with the following two characteristics:  The range is not symmetrical, there is one more negative number than there are positive numbers.  There is only one pattern for zero (-0 and +0 have the same pattern)  Example of Binary RC or 2’s Complement Numbers for a 4-bit word Binary SM Number (n=4) Decimal Number d3 d2 d1 d 0 1 1 1 + 7 = +(24 -1^ -1) 0 1 1 0 + 6 0 1 0 1 + 5 0 1 0 0 + 4 0 0 1 1 + 3 0 0 1 0 + 2 0 0 0 1 + 1 0 0 0 0 + 0 0 0 0 0 - 0 1 1 1 1 - 1 1 1 1 0 - 2 1 1 0 1 - 3 1 1 0 0 - 4 1 0 1 1 - 5 1 0 1 0 - 6 1 0 0 1 - 7 1 0 0 0 -8 == -24 -  Quick Inspection Method  Finding 2’s complement  Working from the LSB of the number to be complemented toward the MSB (right to left), rewrite each bit up to and including the first “1” encountered, then complement each bit thereafter  Example: MSB LSB Old Number: (1 0 1 1 0 1 0) 2’s Complement: (0 1 0 0 1 1 0) **Note: 2’s complement gets you back to the original number.

(+5) 10 = (0 1 0 1 )2RC

( -5) 10 = -(0 1 0 1)2RC

Bit-invert  1 0 1 0 Add 1  + 1

---

2’s Compl.  (1 0 1 1)2RC One Sign Bit 0  + 1  - 3 Magnitude Bit

1.8. Binary Arithmetic

All of today’s computer systems use RC numbers (2’s complement) for binary arithmetic operations. The reset of this section provides description of Binary Arithmetic using RC numbers.  Addition of Signed Binary Numbers When adding RC numbers, simply add then ignore the left-most carry. +7  0 1 1 1 +(-2)  1 1 1 0

---

0 1 0 1 “Ignore the left-most carry, and the result is +5” Notes:  The left-most bit is a sign bit and there are three magnitude bits.  As long as we know results fits within the 1 sign-bit and n magnitude bits, this process works. Otherwise we need to consider the overflow.  Addition of Unsigned Binary Numbers Unsigned addition Signed works exactly the same way as singed addition, allowing us to use the same circuitry. +7  0 1 1 1 +3  0 0 1 1

---

1 0 1 0 “Result is +10. If there is a carry beyond the available bits, then an an overflow has occurred.  Overflow  An overflow occurs when the addition of two numbers results in a number larger than can be expressed with the available number of bits.  Example – performing the operation, 8+9=17; in a 4-bit word system, results in an overflow since 4 bits can only store 0 to 15. The result will show as a 1, which is 16 less than the correct result.  Detecting overflow  Unsigned number addition If the addition has a carry beyond the available bits then an overflow has occurred.  Signed (RC, 2’s complement) number addition  If the operands have different signs, then overflow cannot occur, since one number is being subtracted from the other.  If the operands have the same sign and the result has a different sign, then an overflow has occurred. A quick way to identify an overflow situation is when the carry into the sign-bit position and the carry out of sign-bit position are different. Example