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UNIT 6
ARITHMETIC
Addition and subtraction are basic operations performed on digital computer. The Arithmetic and Logic Unit (ALU) performs these operations along with other logical operations like AND, OR, NOT, XOR.
6.1 Addition and Subtraction of Signed Numbers
Let X and Y be any two n bit numbers and xi and yi be the ith^ bit respectively in both numbers. Let Ci be the carry coming from (i – 1) thstage of addition of Xi-1 and Yi-1. The various possibilities are shown below: xi yi Carry-in Ci^ Sum Si^ Carry Ci+1-out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Sum(Si) Logic
If you notice carefully Sum (Si) bit is 1 (i.e. ON) in 4 scenarios. Scenario 1: xi = 0,yi=0 and Ci=1 i.e.x𝑖 𝑦𝑖 𝑐𝑖 Scenario 2: xi =0, yi=1 ,Ci=0 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 Scenario 3: xi = 1, yi=0, Ci=0 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 Scenario 4: xi = 1, yi= 1, Ci=1 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 Hence, Si =x𝑖 𝑦𝑖 𝑐𝑖 + 𝑥𝑖 𝑦𝑖 𝑐𝑖 +𝑥𝑖 𝑦𝑖 𝑐𝑖 +𝑥𝑖 𝑦𝑖 𝑐𝑖 (Note: The + refers to “OR” and not arithmetic „+‟) In short, Si = 𝒙𝒊 𝒚𝒊 𝒛𝒊 i.e. xi XOR yiXOR Ci
Carry (Ci) Logic You will notice that carry is 1 in following scenarios Scenario 1: xi = 0,yi=1 and Ci=1 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 or 𝑦𝑖 𝑐𝑖 Scenario 2: xi = 1,yi=0 and Ci=1 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 or 𝑥𝑖 𝑐𝑖 Scenario 3: xi = 1,yi=1 and Ci=0 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 or 𝑥𝑖 𝑦𝑖 Scenario 4: xi = 1,yi=1 and Ci=1 i.e. 𝑥𝑖 𝑦𝑖 𝑐𝑖 Now, Scenario 3 and Scenario 4 can be shown by single equation i.e. 𝑥𝑖 𝑦𝑖 Hence, carry is generated when 𝑐𝑖+1 = 𝑦𝑖 𝑐𝑖 + 𝑥𝑖 𝑐𝑖 + 𝑥𝑖 𝑦𝑖 Circuits for Si and Ci+
Both the above circuits can be put together and shown as a full adder (FA) as below:
Figure 6.2a: Logic for a single stage
The above figure represents addition of two one bits. However, numbers are n bit long. Hence , a cascaded full adder is required to add two “n” bit number X and Y. Such a cascaded circuit where carry bit ripples from one FA to another is called a “ n bit ripple-carry adder ” as shown below.
Figure 6.2b: An n-bit ripple-carry adder Suppose we need to add k such n bit number. (Ex If n=8 and we want to add two 32-bit numbers then we will need 4 such ripple address) So, a k n-bit adder is shown as:
6.1.1 Addition/Subtraction Logic Unit
Addition: Addition of 2n bit numbers is fairly straight forward: Step 1: Obtain 2‟s complement of X (X is n bit numbers) Step 2: Obtain 2‟s complement of Y (Y is n bit numbers) Step 3: Use Fig 6.2 (b) to add these numbers. Co will be equal to 0 in this case. Xn-1 and Yn-1 shall be the sign bits (MSB)
Detecting overflow during Addition(Method 1) Let‟s recall showing when an overflow can occur:
Sum is 1000 (There is an overflow as MSB bit is 1 for result)
Sum is 0111 (There is an overflow as MSB bit is 0 for result)
The problem with overflow is that the sum has a different sign compared to operands Note: Overflow is seen when xn-1 = 0, yn-1 = 0 and Sn-1 = 1 i.e. 𝑋𝑛− 1 𝑌𝑛− 1 𝑆𝑛− 1 or xn-1 = 1, yn-1 = 1 and Sn-1 = 0 i.e.𝑋𝑛− 1 𝑌𝑛− 1 𝑆𝑛− 1
A circuit to detect overflow can be written as: 𝑂𝑣𝑒𝑟𝑓𝑙𝑜𝑤 = 𝑋𝑛− 1 𝑌𝑛− 1 𝑆𝑛− 1 + 𝑋𝑛− 1 𝑌𝑛− 1 𝑆𝑛− 1
Detecting overflow during Addition (Method 2) If Carry(Cn-1) and Carry (Cn) are different then an overflow has occurred
The XOR gate at “Y” converts Y to 1‟s complement of Y. The “Add/Sub Control” which results in Carry C 0 bit to be 1. So this bit further adds 1 to the sum resulting in 2‟s complement of Y. Hence X and Y are essentially subtracted.
6.2 Design of Fast Adders:
In the n-bit ripple carry adder, by the time the complete sum is calculated, a significant amount of delay is
observed. There are three sources of delay. (a) At each full adder, calculation has to go through one XOR for sum and another for carry.
Hence, for “n” bit addition the number of gate through which the bits have to pass = 2n. (b) Additionally at “y‟ calculation an XOR logic is applied(Fig 6.3).This adds 1 to the gate count.
(c) To take care of the carry issue(Cn (^) Cn-1) one more gate logic is required.
Hence, number of gate logic circuits that are required before the sum is finally computed is 2n+2.
There are two ways to reduce the delay.
(a) Implement the n bit ripple carry using latest fastest possible electronic technology. (b) Use a gate logic that is larger than Fig 6.2b.
6.2.1 Carry-Look Ahead Addition
We know that the sum and carry for ith^ x and y bits is represented as Si = 𝒙𝒊 𝒚𝒊 𝒛𝒊and Ci+1 = xiyi + xiCi + yiCi
The above equation can be written as Ci+1 = xiyi + (xi + yi) Ci If we represent Gi = xiyi and Pi = xi + yi, Then Ci+1 = Gi + PiCi Gi is called Generate and Pi is called Propagate.
We can write Pi = xi yi instead of Pi = xi + yi and still Ci+1 will hold good, because of following reason. Xi Yi xi+yi xi yi 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 Note: + ->OR and ->XOR Only difference is the last row, where xi yi gives 0 instead of 1 but this is compensated by Gi i.e. xiyi = 1.1 = 1 leading to Ci = 1+ 0 = 1. Hence, we can write Ci+1 = Gi + PiCi where Gi = xiyi Pi=xi Yi and we know Si = xi Yi Ci So, we can write the basic cell for a single bit adder as below.
We can recursively write Ci+1 as below Ci+1 = Gi + PiCi =Gi + Pi[Gi-1 + Pi-1Ci-1] =Gi + PiGi-1 + PiPi-1Ci- = Gi + PiGi-1 + PiPi-1[Gi-2+ Pi-2Ci-2] =Gi + PiGi-1 + PiPi-1Gi-2 + PiPi-1Pi-2Ci- Ci+1 = Gi + PiGi-1 + PiPi-1Gi-2+…..+PiPi-1….P 1 G 0 + PiPi-1…P 0 C 0 One will notice one important thing: to calculate thei+1th, carry you only need C 0 .You don‟t need the chain now.
As soon as you apply the value of X,Y and C 0 the sum is obtained in 3 gate delay (instead of n gate delay) as below: o One gate delay to calculate ALL Pi and Gi o One gate delay for AND logic (ex PiGi-1) o One more gate delay to do the OR logic (ex: Gi + PiGi + … + … + ) Hence, in 3 gate delay we get the carry. o For sum we need to do one final XOR. Hence One more XOR for sum Hence, the sum is obtained in four gate delays.
A 4-bit carry-lookahead adder circuit is given in the following figure:
The carry C 1 , C 2 , C 3 , C 4 can be represented in terms of G and P as below: C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 The above circuit is called a carry-lookahead adder. Carry-lookahead circuit calculates C 1 ,C 2 ,C 3 ,C 4 using Pi and Gi. This circuit uses 3 gate delays for all carry and 4 gate delays for sum. In comparison the 4 – bit ripple carry adder uses 7 gate delays for S 3 and 8 gate delays for C 4. Multiple 4 bit carry look ahead adder can be used to implement n-bit address. For example: Eight 4-bit adders can be connected together to form a 32-bit adder. In this case sum S 31 and carry C 32 are available after 63 and 64 gate delays respectively.
Higher – level Generate and Propagate Function The figure below shows the 16-bit carry – look ahead adder built using 4-bit adders.
The square box represents a single cell that implements partial product for one bit as shown:
o Each row i, where 0 ≤ i ≤ 3 adds the multiplicand to the incoming partial product, PPi to generate the outgoing partial product, PP(i+1), if qi=1. However, if qi=0, PPi is passed vertically downwards unchanged. o Note: The worst case signal propagation delay path is from the upper right corner of the array to the higher order product bit at the bottom left corner of array. o The path has a total of 6(n-1)-1 gate delays including initial AND gate delay in all cells for n X n array.
The other method to perform multiplication is to use the adder circuitry in the ALU for a number of
sequential steps. The figure below shows the sequential circuit binary multiplier:
Now, let‟s take the example as before: M = 1101, A = 0000, Q = 1011, C = 0 As per above circuit diagram the following has to be done Step 1: Add M and A (only if LSB of Q i.e. q 0 = 1). Step 2: Store the result in A and carry bit(if any in C) Step 3: Shift by 1 bit the pattern “C A Q”
Round 1 Step 1: Add M and A (only if q 0 =1. Since q 0 =1 we can add M and A).
Step 2: Store the result in A and carry = 0 in C
Step 3: Shift right by 1 bit the C A Q value. New values in C A and Q after shift right by 1 bit is
Round 2:
Step 1: Add M and A only if q 0 =1. This is true
Step 2: Store the values in “C” and “A” (i.e. sum and carry generated in step 1)
Step 3: Shift right “C” and “Q” by 1 bit. So, the value of “C” “A” and “Q” after shifting right is
Round 3
Step 1: Add M and A if q 0 = 1 This condition fails so no addition done (q 0 ≠ 1) Step 2: The sum and carry generated in Step 1 are stored in “C” and “A” Note: Since no sum was done, so no new values are updated for “C” and “A” so “C”, “A” and “Q” values remain as in step 3 of round 2.
Step 3: Shift right by 1 “C” “A” and “Q”
Round 4: Step 1: Add M and A if q 0 =
Step 2: The sum and carry generated in Step 1 are copied to “A” and “C” respectively.
Step 3: Shift right by 1 bit “C”, “A” and “Q”. Hence, the values in C A and Q after shifting right is:
Final answer:
The values in A and Q concatenated together to form the product
The above steps can be written in the following table to visualize in one shot.
Booth algorithm can be visualized using following steps:
Let Multiplicand = 0101101 Multiplier = 0011110
Step 1: Put a 0 at the end of multiplier 00111100 extra 0 at the end Step 2: Start from right side and take 2 bits at a time. Look at the table and pick the appropriate value. Ex: For above multiplier (0011110), the new multiplier is calculated as:
So, the new multiplier is Step 3: Now, perform the multiplication keeping in mind that:
If -1 is the multiplier then partial sum will be 2‟s complement of multiplicand If multiplier is 0, partial sum will be all 0‟s If multiplier is 1, then partial sum will be the multiplicand.
Calculations are done as shown in below example:
In the above example we notice that when “-1” was encountered the partial sum was 2‟s complement of multiplicand.
Example: Another example here the multiplier is negative. 01101 (+13) 11010 (-6) Solution: Step 1: Put a 0 at the end of multiplier. So the multiplier is 110100. Step 2: Start from right side, pick 2 bits at a time and based on table generate a new multiplier calculated as below:
Step 3: Apply below logic If multiplier bit is 0, then partial sum is all 0‟s If multiplier bit is +1 then partial sum is same as multiplicand If multiplier bit is -1 then partial sum is 2‟s complement of multiplicand
Worst case, ordinary, Best Case multiplier A multiplier is a worst case multiplier if it has alternate 0‟s and 1‟s.The resulting multiplier after applying the table will contain alternate +1 and -1 as below.
A multiplier with a bunch of 0‟s and 1‟s is a best case/good multiplier.
An ordinary multiplier has random bunch of 0‟s and/or 1‟s.
6.5 Fast Multiplication
Bit-Pair Recoding of Multipliers
- Group the booth recoded multiplier bits in pairs, and it can be observed, that, the pair (+1, -1) is same to the pair (0, +1), i.e., Instead of adding -1 x M at shift position i with +1 x M at i+1, it can be added with +1 x M at position i.
- Bit-pair recoding halves the maximum number of summands (versions of the multiplicand).
The delay through the carry-save array is somewhat less than delay through the ripple-carry array. This is because the S and C vector outputs from each row are produced in parallel in one full-adder delay. Consider the addition of many summands, we can: Group the summands in threes and perform carry-save addition on each of these groups in parallel to generate a set of S and C vectors in one full-adder delay Group all of the S and C vectors into threes, and perform carry-save addition on them, generating a further set of S and C vectors in one more full-adder delay
Continue with this process until there are only two vectors remaining. They can be added in a RCA or CLA to produce the desired product.
When the number of summands is large, the time saved is proportionally much greater. Delay: AND gate + 2 gate / CSA level + CLA gate delay, E.g., 6 bit number require 15 gate delay, array 6x6 require 6(n-1)-1 =29 gate D. In general CSA takes 1.7 log2 k -1.7 levels of CSA to reduce k summands.
6.6 Integer Division
Let‟s take a decimal division:
The same division in binary is as below:
Round 2: Step 1: Shift A and Q left one binary position so new A Q is:
Step 2: Subtract M from A (i.e. add 2‟s complement of M to A)
New A Step 3: If sign of A is 1(yes MSB of A is 1) so set q 0 to 0, hence
Add M to A so that we can restore back A i.e. add 00011 to 11111
At this point:
Round 3: Step 1: Shift A and Q left by one position. So new value of A and Q are
Step 2: Subtract M from A (i.e. add 2‟s complement of M to A)
Step 3: If sign of A is 0 (yes MSB of A is 0) then just set q 0 to 1.
Round 4: Step 1: Shift A and Q left by one position. So new value of A and Q are
Step 2: Subtract M from A (i.e. add 2‟s complement of M to A)
New A Step 3: If sign of A is 1 (which is true), then Add M to A(i.e. restore A) and set q 0 to 0.
Q = 0 0 1 0
Hence after 4 rounds we have the, remainder in A i.e. 00010 and Quotient is Q i.e. 0010
The above steps can be written as below:
Non-restoring Division: Non-restoring division algorithm does the following
Step 1: Do the following “n” times. o If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift A and Q left and add M to A. o Now, if the sign of A is 0, set q 0 to 1; otherwise, set q 0 to 0. Step 2: If the sign of A is 1, add M to A.
Example: Let‟s take the same example Solution: Initially A=00000 M= 00011 Q =
Let us do the Step 1 “n” number of times (“n” here is 4 so 4 rounds are done for step 1)
Round 1: Sign of A is 0 so shift AQ left by 1 position and subtract M from A.
A-M gives the following:
New A Sign of A is 1, so set q 0 to 0. Hence,
Round 2: Sign of A is 1 Shift AQ left by 1 bit and add M to A.
A+M gives the following:
6.7 Floating-Point Numbers and Operations
A floating point number can be represented in 2‟s complement system as
B = b 0 .b-1 b-2 b-3….b-(n-1)
Ex: 1.001011, 1. We can get back the number in decimal from at As F(B) = -b 0 x 2^0 + b-1 x 2-1^ + b-2 x 2-2+…..+ b-(n-1) x 2-(n-1) For Example: 1.001011 -1 x 2^0 + 0 x 2-1^ + 0 x2-2^ + 1 x 2-3^ + 0 x 2-4^ + 1 x 2-5^ + 1 x 2- Here -1≤ F≤ 1-2-(n-1) If we have a 32-bit location then we can store a floating point number in the range ±4.55 × 10−^10 𝑡𝑜 ± 1
6.7.1 IEEE Standard for Floating-Point Numbers
Before we look at the way IEEE represents a floating point number, we will look at the meaning of normalized and unnormalized version.
Normalized: The floating point number where the point appears after first number/bit.
Unnormalized: The floating point number where the point appears anywhere in the number.
Ex: +1.0110 x2^6 Normalized +0.0010110x2^9 Unnormalized
For binary number we can convert an “unnormalized” number to normalized number by shifting the decimal point next to first number/bit and incrementing the power of 2.
Ex 1: 0.00001101 which is an unnormalized number can be written in normalized form as 1.101x2- Ex 2: 1101000.1101 can be written in normalized form as 1.1010001101x2^6
If you observe carefully we move the point till we find the first “1”. In ex 1 we move to right till we find the first “1” and then we stop.
The way we represent the unnormalized and normalized number is
Normalized representation / value:
A fairly precise floating point number looks as below:
- X 1 .X 2 X 3 X 4 X 5 X 6 X 7 X 10 x 10 ±𝑌^1 𝑌^2 Here Xi and Yi are decimal number (i.e. 0-9)
Note that digits are 7 i.e. from X 1 to X 7 , and exponent range is ±99 ie -99 ≤ y 1 y 2 ≤ 99 Ex 0.194579 x 10^45 , 1.742116 x 10-30, 8.123456 x 10^30 If we have to store a binary representation of these numbers (floating number with + significant digits with exponent range +99). In a 32- bit representation then we need space for o 24 bit mantissa can approximately hold 7-digit decimal number (M) o 8-bit exponent can hold a reasonable range (E‟)
o 1 bit for sign (+ or-) (S)
IEEE floating point for 32-bit (single precision) is as shown below:
The value that above figure represents is a binary number in the range = +1.M x 2E‟-
Ex: Suppose that I want to store 1.001010…0 x 2 -87^ in a 32 bit word then I do the following. Solution: S=0 (sign bit is 0 because it is a +ve number) E‟ = E + 127 (or E=E‟ -127) E‟ = -87 + 127 = 40 = 00101000 M = 001010…0 (from the problem itself i.e. number after decimal point) So, 1.001010…0 x 2-87^ is stored in 32 bits. 0 00101000 001010……..
Ex: Suppose I want to store 1.111100….0 x 2- Solution: S = 0 (+ve number so sign bit is 0) E‟ = E + 127 = -126 + 127 = 1 = 00000001 (there are 8 bits for E‟) M = 111100….0 (all numbers after decimal point). 0 00000001 111100…
Ex: Suppose the 32 bit memory contains the following, then what is the value. 0 00000011 011010… Solution: S = 0 (+ve number) E‟ = 0000011 = 3 So, E = E‟ – 127 = 3 – 127 = - M = 011010 Hence, the memory is storing 1.011010 x 2-
Note : In all the above examples the number “1” is added implicitly to the number. This is not stored anywhere. For a number in normalized form, the number on the left of decimal point is always 1.
Double Precision: The 32 bit representation described above has a range of 2-126^ to 2+127^ i.e. decimal number in the range of 10 -38^ to 10+38^ can be stored at the maximum. If we want to store higher range between 2-1022^ to 2+1023^ (i.e. in decimal numbers between 10-308^ to 10^308 ) then the length of the word has to be 64 bits with the following split: o Sign bit = 1 bit o Exponent = 11 bits (Excess -1023 component) o Mantissa = 52 bits
