Download Computer Components & Instruction Execution: Control Unit, CPU, & Memory and more Exams Architecture in PDF only on Docsity!
COMPUTER ORGANIZATION AND ARCHITECTURE
Computer Architecture refers to those attributes of a system that have a direct impact on
the logical execution of a program. Examples:
o the instruction set
o the number of bits used to represent various data types
o I/O mechanisms
o memory addressing techniques
Computer Organization refers to the operational units and their interconnections that
realize the architectural specifications. Examples are things that are transparent to the
programmer:
o control signals
o interfaces between computer and peripherals
o the memory technology being used
So, for example, the fact that a multiply instruction is available is a computer architecture
issue. How that multiply is implemented is a computer organization issue.
- Architecture is those attributes visible to the programmer
o Instruction set, number of bits used for data representation, I/O mechanisms,
addressing techniques.
o e.g. Is there a multiply instruction?
- Organization is how features are implemented
o Control signals, interfaces, memory technology.
o e.g. Is there a hardware multiply unit or is it done by repeated addition?
- All Intel x86 family share the same basic architecture
- The IBM System/370 family share the same basic architecture
- This gives code compatibility
o At least backwards
- Organization differs between different versions
STRUCTURE AND FUNCTION
- Structure is the way in which components relate to each other
- Function is the operation of individual components as part of the structure
- All computer functions are:
o Data processing : Computer must be able to process data which may take a wide
variety of forms and the range of processing.
o Data storage : Computer stores data either temporarily or permanently.
o Data movement : Computer must be able to move data between itself and the
outside world.
o Control : There must be a control of the above three functions.
Fig: Functional view of a computer
Fig: Data movement operation Fig: Storage Operation
Fig: Processing from / to storage Fig: Processing from storage to i/o
- Four main structural components: o^ Central processing unit (CPU)
Control Unit
CPU
Sequencing
ALU
Internal (^) Control Login
Bus Control Unit
Unit
Registers Registers and
Decoders
Control
Fig: The control unit Memory
COMPUTER COMPONENTS
- The Control Unit (CU) and the Arithmetic and Logic Unit (ALU) constitute the Central
Processing Unit (CPU)
- Data and instructions need to get into the system and results need to get out
o Input/output (I/O module)
- Temporary storage of code and results is needed
o Main memory (RAM)
o Hardwired systems are inflexible
o General purpose hardware can do different tasks, given correct control signals
o Instead of re-wiring, supply a new set of control signals
Fig: Example of program execution (consists of memory and registers in hexadecimal)
- The PC contains 300, the address of the first instruction. The instruction (the value 1940
in hex) is loaded into IR and PC is incremented. This process involves the use of MAR
and MBR.
- The first hexadecimal digit in IR indicates that the AC is to be loaded. The remaining
three hexadecimal digits specify the address (940) from which data are to be loaded.
- The next instruction (5941) is fetched from location 301 and PC is incremented.
- The old contents of AC and the contents of location 941 are added and the result is stored
in the AC.
- The next instruction (2941) is fetched from location 302 and the PC is incremented.
- The contents of the AC are stored in location 941.
Fig: Instruction cycle state diagram
BUS INTERCONNECTION
- A bus is a communication pathway connecting two or more devices
- Usually broadcast (all components see signal)
- Often grouped
o A number of channels in one bus
o e.g. 32 bit data bus is 32 separate single bit channels
- Power lines may not be shown
- There are a number of possible interconnection systems
- Single and multiple BUS structures are most common
- e.g. Control/Address/Data bus (PC)
- e.g. Unibus (DEC-PDP)
- Lots of devices on one bus leads to:
o Propagation delays
o Long data paths mean that co-ordination of bus use can adversely affect
performance
o If aggregate data transfer approaches bus capacity
- Most systems use multiple buses to overcome these problems
o Carries data
Remember that there is no difference between “data” and “instruction” at this
level
o Width is a key determinant of performance
8, 16, 32, 64 bit
o Identify the source or destination of data
o e.g. CPU needs to read an instruction (data) from a given location in memory
p Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space
q Control and timing information
Memory read
Memory write
I/O read
I/O write
Transfer ACK
Bus request
Bus grant
Interrupt request
Interrupt ACK
Clock
Reset
Multiple Bus Hierarchies
A great number of devices on a bus will cause performance to suffer
o Propagation delay - the time it takes for devices to coordinate the use of the bus
o The bus may become a bottleneck as the aggregate data transfer demand approaches
the capacity of the bus (in available transfer cycles/second)
Traditional Hierarchical Bus Architecture
o Use of a cache structure insulates CPU from frequent accesses to main memory
o Main memory can be moved off local bus to a system bus
o Expansion bus interface
buffers data transfers between system bus and I/O controllers on expansion bus
insulates memory-to-processor traffic from I/O traffic
Note: Bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s
I/O capability.
PCI Bus Lines
o Including clock and reset
o 32 time mux lines for address/data
o Interrupt & validate lines
- Interface Control
- Arbitration
o Not shared
o Direct connection to PCI bus arbiter
o Not shared
- Cache support
- 64 - bit Bus Extension
o Additional 32 lines
o Time multiplexed
o 2 lines to enable devices to agree to use 64-bit transfer
o For testing procedures
CPU REGISTERS
In computer architecture , a processor register is a very fast computer memory used to speed the
execution of computer programs by providing quick access to commonly used values-typically, the values
being in the midst of a calculation at a given point in time.
These registers are the top of the memory hierarchy, and are the fastest way for the system to manipulate
data. In a very simple microprocessor , it consists of a single memory location, usually called
an accumulator. Registers are built from fast multi-ported memory cell. They must be able to drive its
data onto an internal bus in a single clock cycle. The result of ALU operation is stored here and could be
re-used in a subsequent operation or saved into memory.
Registers are normally measured by the number of bits they can hold, for example, an “8-bit register” or a
“32-bit register”. Registers are now usually implemented as a register file, but they have also been
implemented using individual flip-flops, high speed core memory, thin film memory, and other ways in
various machines.
The term is often used to refer only to the group of registers that can be directly indexed for input or
output of an instruction, as defined by the instruction set. More properly, these are called the “ architected
registers “. For instance, the x86 instruction set defines a set of eight 32-bit registers, but a CPU that
implements the X86 instruction set will contain many more hardware registers than just these eight.
There are several other classes of registers:
(a) Accumulator : It is most frequently used register used to store data taken from memory. Its number
varies from microprocessor to microprocessor.
(b) General Purpose registers : General purpose registers are used to store data and intermediate results
during program execution. Its contents can be accessed through assembly programming.
(c) Special purpose Registers : Users do not access these registers. These are used by computer system at
the time of program execution. Some types of special purpose registers are given below:
Memory Address Register (MAR ): It stores address of data or instructions to be fetched from
memory.
Memory Buffer Register (MBR) : It stores instruction and data received from the memory and
sent from the memory.
Instruction Register (IR): Instructions are stored in instruction register. When one instruction is
completed, next instruction is fetched in memory for processing.
Program Counter (PC): It counts instructions.
Most computers fall into one of 3 types of CPU organizations:
Single accumulator organization:- All the operations are performed with an
accumulator register. The instruction format in this type of computer uses one address
field. For example: ADD X, where X is the address of the operands.
General register organization:- The instruction format in this type of computer needs
three register address fields. For example: ADD R1,R2,R
Stack organization :- The instruction in a stack computer consists of an operation code
with no address field. This operation has the effect of popping the 2 top numbers from the
stack, operating the numbers and pushing the sum into the stack. For example: ADD
Computers may have instructions of several different lengths containing varying number of
addresses. Following are the types of instructions.
1. Three address Instruction
With this type of instruction, each instruction specifies two operand location and a result
location. A temporary location T is used to store some intermediate result so as not to
alter any of the operand location. The three address instruction format requires a very
complex design to hold the three address references.
Format: Op X, Y, Z; X Y Op Z
Example: ADD X, Y, Z; X Y + Z
ADVANTAGE: It results in short programs when evaluating arithmetic
expressions.
DISADVANTAGE: The instructions requires too many bits to specify 3
addresses.
2. Two address instruction
Two-address instructions are the most common in commercial computers. Here again
each address field can specify either a processor register, or a memory word. One address
must do double duty as both operand and result. The two address instruction format
reduces the space requirement. To avoid altering the value of an operand, a MOV
instruction is used to move one of the values to a result or temporary location T, before
performing the operation.
Format: Op X, Y; X X Op Y
Example: SUB X, Y; X X - Y
3. One address Instruction
It was generally used in earlier machine with the implied address been a CPU register
known as accumulator. The accumulator contains one of the operand and is used to store
the result. One-address instruction uses an implied accumulator (Ac) register for all data
manipulation. All operations are done between the AC register and a memory operand.
We use LOAD and STORE instruction for transfer to and from memory and Ac register.
Format: Op X; Ac Ac Op X
Example: MUL X; Ac Ac * X
4. Zero address Instruction
It does not use address field for the instruction like ADD, SUB, MUL, DIV etc. The
PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack. The name “Zero” address is given because of the absence
of an address field in the computational instruction.
Format: Op; TOS TOS Op (TOS – 1)
Example: DIV; TOS TOS DIV (TOS – 1)
Example: To illustrate the influence of the number of address on computer programs, we will
evaluate the arithmetic statement X=(A+B)*(C+D) using Zero, one, two, or three address
instructions.
- Three-Address Instructions:
ADD R1, A, B; R1 M[A] + M[B]
ADD R2, C, D; R2 M[C] + M[D]
MUL X, R1,R2; M[X] R1 * R
It is assumed that the computer has two processor registers R1 and R2. The symbol M[A]
denotes the operand at memory address symbolized by A.
- Two-Address Instructions:
MOV R1, A; R1 M[A]
ADD R1, B; R1 R1 + M[B]
MOV R2, C; R2 M[C]
ADD R2, D; R2 R2 + M[D]
MUL R1, R2; R1 R1 * R
MOV X, R1; M[X] R
- One-Address Instruction:
LOAD A; Ac M[A]
ADD B; Ac Ac + M[B]
STORE T; M[T] Ac
LOAD C; Ac M[C]
ADD D; Ac Ac + M[D]
MUL T; Ac Ac * M[T]
STORE X; M[X] Ac
Here, T is the temporary memory location required for storing the intermediate result.
- Zero-Address Instructions:
PUSH A; TOS A
PUSH B; TOS B
ADD; TOS (A + B)
PUSH C; TOS C
PUSH D; TOS D
ADD; TOS (C + D)
MUL; TOS (C + D) * (A + B)
POP X ; M[X] TOS
immediate-mode instruction has an operand field rather than an address field.
This instruction has an operand field rather than an address field. The operand field
contains the actual operand to be used in conjunction with the operation specified in the
instruction.
These instructions are useful for initializing register to a constant value;
For example MVI B, 50H
Instruction
It was mentioned previously that the address field of an instruction may specify either a memory
word or a processor register. When the address field specifies a processor register, the instruction
is said to be in register-mode.
Advantage: no memory reference. Disadvantage: limited operand
Register direct addressing mode:
In this mode, the operands are in registers that reside within the CPU.
The particular register is selected from the register field in the instruction.
For example MOV A, B
Instruction
Register
Operand
Effective Address (EA) = R
Advantage: no memory reference. Disadvantage: limited address space
Register indirect addressing mode:
In this mode the instruction specifies a register in the CPU whose contents give the
address of the operand in the memory.
In other words, the selected register contains the address of the operand rather than the
operand itself.
Before using a register indirect mode instruction, the programmer must ensure that the
memory address of the operand is placed in the processor register with a previous
instruction.
For example LDAX B
Instruction
Register
Memory
Operand
Effective Address (EA) = (R)
Advantage: Large address space.
Opcode Operand
Opcode Register
Opcode Register
The address field of the instruction uses fewer bits to select a register than would have been
required to specify a memory address directly.
Disadvantage: Extra memory reference
Auto increment or Auto decrement Addressing Mode :
This is similar to register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
When the address stored in the registers refers to a table of data in memory, it is
necessary to increment or decrement the registers after every access to the table.
This can be achieved by using the increment or decrement instruction. In some computers
it is automatically accessed.
The address field of an instruction is used by the control unit in the CPU to obtain the
operands from memory.
Sometimes the value given in the address field is the address of the operand, but
sometimes it is the address from which the address has to be calculated.
Direct Addressing Mode
In this mode the effective address is equal to the address part of the instruction. The
operand resides in memory and its address is given directly by the address field of the
instruction.
For example LDA 4000H
Instruction
Memory
Operand
Effective Address (EA) = A
Advantage: Simple. Disadvantage: limited address field
Indirect Addressing Mode
In this mode the address field of the instruction gives the address where the effective
address is stored in memory.
Control unit fetches the instruction from the memory and uses its address part to access
memory again to read the effective address.
Instruction
Memory
Effective Address (EA) = (A)
Advantage: Flexibility. Disadvantage: Complexity
Displacement Addressing Mode
Operand
Opcode Address
Opcode Address
last in First out (LIFO) queue. The stack pointer is maintained in register.
Instruction
Implicit
Top of Stack
Effective Address (EA) = TOS
Let us try to evaluate Example.
Fig: Numerical Example for Addressing Modes
Fig: Tabular list of Numerical Example
DATA TRANSFER AND MANIPULATION
Data transfer instructions cause transfer of data from one location to another without changing
the binary information. The most common transfer are between the
Memory and Processor registers
Processor registers and input output devices
Processor registers themselves
Typical Data Transfer Instructions
DATA MANIPULATION INSTRUCTIONS
Data manipulation instructions perform operations on data and provide the computational
capabilities for the computer. These instructions perform arithmetic, logic and shift
operations.
Arithmetic Instructions
