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ECS 50: Computer Organization and ECS 50: Computer Organization and
MachineMachine--Dependent ProgrammingDependent Programming
Spring 2008 Spring 2008
Shoukat Ali [email protected]
Interrupts, Interrupt Service Interrupts, Interrupt Service
Subroutines (Subroutines (ISRsISRs), and Such), and Such
Handout 14
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Device Controllers and Input/Output Ports Device Controllers and Input/Output Ports
each device (keyboard, printer etc) has an device controller associated with it
each device controller maintains a set of device registers
command register (write-only) status register (read-only) data register (read/write)
these registers are 8-bits wide and are also known as i/o ports
special I/O instructions give CPU access to I/O ports
INB AAA --- ACC[7-0] = port[AAA] OUTB AAA --- port[AAA] = ACC[7-0]
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Keyboard Example: Using Status and Data Registers Keyboard Example: Using Status and Data Registers
characters typed in are saved in a 10-char queue; initially empty
when a character arrives in the queue, keyboard controller
puts the character at the head of queue in the data register sets the MSB of its status register to 1 (LT = MSB)
CPU can continually check the status register, and will read data register when data is ready
.EQU KBD_STAT, $
.EQU KBD_DATA, $
POLL: INB KBD_STAT
JGE POLL
INB KBD_DATA
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Keyboard Example: Using Control RegisterKeyboard Example: Using Control Register
if some character read by the CPU does not make any sense, then the CPU might want to get rid of the entire keyboard buffer
this is accomplished by writing a 1 to the second MSB of control register (at address $000) note this address is shared by the status register
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CUSP Timer: Addresses Of Timer Register CUSP Timer: Addresses Of Timer Register
timer control register is write only address is $ timer status register is read only address is $
it is OK for control register and status register to have the same address because the hardware internally ensures that
timer reload value register: addr $
status register
control register
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Example OperationExample Operation
program
must reset
ready bit if
it wants
another
alarm after
80 cycles
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Bit Assignments For Timer Registers (AKA Ports) Bit Assignments For Timer Registers (AKA Ports)
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Timer ProgramTimer Program That Beeps EveryThat Beeps Every 1000 Cycles1000 Cycles
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Interrupts AndInterrupts And ISRsISRs
an interrupt is a signal that
automatically interrupts the routine fetch-decode-execute cycle
dumps a new instruction called INT into IR
INT instruction makes the program jump to the address of an “interrupt service subroutine” (ISR)
ISR for a keyboard knows what to do when keyboard interrupts
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ISRsISRs and Interrupt Vectorsand Interrupt Vectors
for each i/o device, its ISR can be anywhere in the memory
however, the address of the associated ISR must be stored at a location known to hardware
CUSP has dedicated the memory locations $FF8 to $FFB for housing the addresses of the ISRs for i/o devices
it is the programmer’s responsibility to write an ISR and put its address in one of the locations below
$FFB addr_of_timer_isr
$FFA addr_of_tape_drive_isr
$FF9 addr_of_printer_isr
$FF8 addr_of_keyboard_isr These four memory locations are called interrupt vectors.
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Interrupt Priorities Interrupt Priorities
which interrupt will be serviced first if all four devices are requesting an interrupt?
computers assign priorities to devices based on their function
CUSP priorities: if all devices interrupt at the same time
a timer interrupt is serviced before any other interrupt
then comes: tape drive, printer, keyboard
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MCQ MCQ
For ISRs to work, what do we need? I. A pre-agreed location where the address of the ISR is written.
II. A mechanism that suspends normal fetch-decode-execute routine when an interrupt arrives.
III. More cow bell.
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FetchFetch
DecodeDecode
ExecuteExecute
CycleCycle
NowNow
new instruction
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INT AAA: Behavior INT AAA: Behavior**
somewhat like a JSR instruction
except that it
saves the flags in addition to the return address resets IE to zero to stop interruptions while this interrupt is being serviced
how do we save the flags?
usually when we push a 12-bit return addr on 24-bit stack, the top 12 bits, N 5 N 4 N 3 , are zero’ed now we set N 5 N 4 to FF, and set the nibble N 3 is allocated for flag storage
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INT AAA: Register TransferINT AAA: Register Transfer**
1111 1111 OELI
PC is stored here
OV is stored here EQ is stored here
LT is stored here
IE is stored here
INT* AAA is equivalent to
- SP = SP – 1
- Mem[SP] = $FF0000 + $008000OV + $004000EQ + $002000*LT + $001000 * IE + PC
- PC = Mem[Mem[AAA]]
- IE = 0
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Returning from an ISR: IRTNReturning from an ISR: IRTN
IRTN instruction is similar to RTN
pops off the flags and return address
PC = Mem[SP] with upper 12 bits somehow reset to 0s = Mem[SP] AND $000FFF
how do we retrieve the flags?
pre-requisite material:
b 3 b 2 b 1 b 0 / 2 = 0b 3 b 2 b 1 0b 3 b 2 b 1 /2 = 00b 3 b 2 00b 3 b 2 / 2 = 000b 3
rule: division by 2x^ brings the bit bx to the LSB position
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Bit Assignments For Timer Registers: Complete PictureBit Assignments For Timer Registers: Complete Picture
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=1000 0000 =0100 0000 =0001 0000 =1101 0000 =1100 0000
add these 3 to get next
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THIS PIECA CODE WILL NOT WORK!
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THIS PIECA CODE WILL NOT WORK!
Why Did the Timer ISR Not Do PSHF, TSF Routine?Why Did the Timer ISR Not Do PSHF, TSF Routine?
subroutines discussed earlier always saved FP and did a TSF
why did this ISR not do that?
