Computer organization lab manual 2018, Study notes of Computer Programming

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COMPUTER ORGANIZATION AND

ARCHITECTURE

LAB MANUAL

DEPARTMENT OF ELECTRICAL ENGINEERING,

FAST-NU, LAHORE

Created by: Tooba Javed & Hina Tariq Date: August 2015 Last Updated by: Maimoona Akram, Awais Khan Date: January 2017 Approved by the HoD: Date:

List of Equipment

Sr. No. Description 1 NASM Compiler 2 AFD Debugger

EXPERIMENT- 1

INTRODUCTION TO THE ASSEMBLER

OBJECTIVES

 How to write a simple assembly language program for x86 (x88) real mode.  How to use the Assembler for editing, assembling and debugging an assembly language program.  How to use the debugger interface for understanding the computer organization.

THEORY

Introduction to the Netwide Assembler (NASM) The Netwide Assembler, NASM, is an 80x86 assembler designed for portability and modularity. It supports a range of object file formats, including Linux and NetBSD/FreeBSD a.out, ELF, COFF, Microsoft 16-bit OBJ and Win32. It will also output plain binary files. Its syntax is designed to be simple and easy to understand, similar to Intel's but less complex. It supports Pentium, P6, MMX, 3DNow, SSE and SSE2 opcodes, and has macro capability. [1] NASM Command-Line Syntax To assemble a file, you issue a command of the form: nasm [infile] [-o outfile] [-l listfile] For example, nasm test.asm – o test.com – l test.lst will assemble test.asm into a .com file test.com and will produce a list file test.lst. By giving the following command help on the nasm features is available: nasm – h With - hf, this will also list the available output file formats, and what they are. The - o Option: Specifying the Output File Name NASM will normally choose the name of your output file for you; precisely how it does this is dependent on the object file format. For Microsoft object file formats (obj and win32), it will remove the .asm extension from your source file name and substitute .obj. For the binary format it will simply remove the extension, so that myfile.asm produces the output file myfile. If the output file already exists, NASM will overwrite it, unless it has the same name as the input file, in which case it will give a warning and use nasm.out as the output file name instead. For situations in which this behavior is unacceptable, NASM provides the - o command-line option, which allows you to specify your desired output file name. You invoke - o by following it with the name you wish for the output file, either with or without an intervening space. For example: nasm - f bin program.asm - o program.com nasm - f bin driver.asm – o driver.sys

The - i Option: Include File Search Directories When NASM sees the %include or incbin directive in a source file, it will search for the given file not only in the current directory, but also in any directories specified on the command line by the use of the - i option. Therefore you can include files from a macro library, for example, by typing nasm - ic:\macrolib\ - f obj myfile.asm (As usual, a space between - i and the path name is allowed and optional). NASM, in the interests of complete source-code portability, does not understand the file naming conventions of the OS it is running on; the string you provide as an argument to the - i option will be prepended exactly as written to the name of the include file. Therefore the trailing backslash in the above example is necessary. The - p Option: Pre-Include a File NASM allows you to specify files to be pre-included into your source file, by the use of the - p option. So running nasm myfile.asm - p myinc.inc is equivalent to running nasm myfile.asm and placing the directive %include "myinc.inc" at the start of the file. For consistency with the - I, - D and - U options, this option can also be specified as - P. NASM Is Case-Sensitive One simple difference is that NASM is case-sensitive. It makes a difference whether you call your label foo, Foo or FOO. If you're assembling to DOS or OS/2 .OBJ files, you can invoke the UPPERCASE directive to ensure that all symbols exported to other code modules are forced to be upper case; but even then, within a single module, NASM will distinguish between labels differing only in case. (Extracted from [1], for more details please see [2]) First Assembly language program: Let us now write a simple assembly language program for a com file which should add two numbers and subtract a third number from the sum, as shown below: ; A PROGRAM TO ADD TWO NUMBERS AND SUBTRACT A THIRD ONE FROM THE SUM ; USING REGISTERS [ORG 0x0100] MOV AX, 5 ; LOAD FIRST NUMBER IN AX MOV BX, 12 ; LOAD SECOND NUMBER IN BX ADD AX, BX ; ACCUMULATE SUM IN AX MOV BX, 14 ; LOAD THIRD NUMBER IN BX SUB AX, BX ; ACCUMULATE SUM IN AX MOV AX, 0x4C00 ; TERMINATE PROGRAM INT 0x

Let us save this in a file named test.asm. Now we use NASM to assemble this program using the command: nasm test.asm – o test.com – l test.lst Which generates two files, test.com and test.lst. Now we will use a debugger to monitor the execution of this program. The debugger we are using is Advanced Fullscreen Debugger (AFD). We will use the load command to load the com file, as shown below. CMD > l test.com As shown in the diagram, the interface of the debugger is easy to understand and use. Using F1 we can step through the code and see the changes taking place in the register contents. PROBLEMS Modify this program to generate the sum of four numbers, using registers, and watch its execution in the debugger. Also explore the various functions available in the debugger (the debugger has built-in context sensitive help).

Post Lab Exercise

Write a program to Add three numbers in Ax register and store the result in Bx register. Also tell the purpose of INT 0X21 statement in our program. REFERENCES 1 http://nasm.sourceforge.net/doc/html/nasmdoc1.html 2 http://nasm.sourceforge.net.

instruction pointer is not directly visible to the programmer; it is controlled implicitly by control- transfer instructions, interrupts, and exceptions. Figure 1 Control Flags

Segment Registers CS Code Segment 16 - bit number that points to the active code-segment DS Data Segment 16 - bit number that points to the active data-segment SS Stack Segment 16 - bit number that points to the active stack-segment ES Extra Segment 16 - bit number that points to the active extra-segment Pointer Registers IP Instruction Pointer 16 - bit number that points to the offset of the next instruction SP Stack Pointer 16 - bit number that points to the offset that the stack is using BP Base Pointer used to pass data to and from the stack General- Purpose Registers AX Accumulator Register mostly used for calculations and for input/output BX Base Register Only register that can be used as an index CX Count Register register used for the loop instruction DX Data Register input/output and used for multiply and divide Index Registers SI Source Index used by string operations as source DI Destination Index used by string operations as destination Figure 2 Summary of Registers

EXPERIMENT- 3

MEMORY SYSTEM

OBJECTIVES

 To be able to do 32 bit computations using 16 bit registers  To learn the x86 memory system segmentation

THEORY

Depending on the machine, a processor can access one or more bytes from memory at a time. The number of bytes accessed simultaneously from main memory is called word length of machine. Generally, all machines are byte-addressable i.e.; every byte stored in memory has a unique address. However, word length of a machine is typically some integral multiple of a byte. Therefore, the address of a word must be the address of one of its constituting bytes. In this regard, one of the following methods of addressing (also known as byte ordering) may be used. Big Endian – the higher byte is stored at lower memory address (i.e. Big Byte first). MIPS, Apple, Sun SPARC are some of the machines in this class. Little Endian - the lower byte is stored at lower memory address (i.e. Little Byte first). Intel’s machines use little endian. Consider for example, storing 0xA2B1C3D4 in main memory. The two byte orderings are illustrated in following figure

Memory Models

In earlier processors like 8080 and 8085 the linear memory model was used to access memory. Flat/ Linear Memory Model – memory appears to a program as a single, contiguous address space of 4GB. Code, data, and stack are all contained in this address space, also called the linear address space 8080 and 8085 could access a total memory of 64K using the 16 lines of their address bus. When designing iAPX88 the Intel designers wanted to remain compatible with 8080 and 8085

however 64K was too small to continue with, for their new processor. The three logical parts of a program (data, code and stack) should appear as three distinct units in memory, but making this division is not possible in the linear memory model. The segmented memory model does allow this distinction. Segmented Memory Model – memory appears to a program as a group of independent memory segments, where code, data, and program stack are contained in separate memory segments. To address memory in this model, the processor must use segment registers and an offset to derive the linear address. The primary reason for having segmented memory is to increase the system's reliability by means of protecting one segment from other. The processor sees code from the code window and data from the data window. The size of one window is restricted to 64K. 8085 software fits in just one such window. It sees code, data, and stack from this one window, so downward compatibility is attained. However the maximum memory iAPX88 can access is 1MB which can be accessed with 20 bits. Compare this with the 64K of 8085 that were accessed using 16 bits. The idea is that the 64K window just discussed can be moved anywhere in the whole 1MB. The four segment registers discussed in the Intel register architecture are used for this purpose. Therefore four windows can exist at one time. For example one window that is pointed to by the CS register contains the currently executing code. Segment Registers The segment registers hold the segment selectors which are special pointers that point to start of individual segments in memory. The use of segment registers is dependent on the memory management model in use. When using the segmented memory model, each segment is loaded with a different memory address as shown in the following figure The segment registers (CS, DS, SS, ES, FS, and GS) hold 16-bit segment selectors. To access a particular segment in memory, the segment selector for that segment must be present in the appropriate segment register. Each of the segment registers is associated with one of three types of storage: code, data, or stack. The DS, ES, FS, and GS registers point to four data segments.

Problems:

1. Fill in the following tables to show storage of 0xABDADDBA at address 1996 in the memory of a machine using (i) little endian (ii) big endian byte ordering.
2. Calculate the physical memory address generated by the following segment offset pairs. a) 1DDD: b) 1234: c) 74F0: d) 0000: e) FFFF:
3. Write instructions to do the following. a. Copy contents of memory location with offset 0025 in the current data segment into AX. b. Copy AX into memory location with offset 0FFF in the current data segment. c. Move contents of memory location with offset 0010 to memory location with offset 00 2F in the current data segment.
4. Write a program to implement 32-bit increment and decrement operations using registers AX and BX. (Hint: Use SBB and ADC) POST LAB Exercise 1) Extend the code in problem – 3, such that your code adds two 32 bit numbers Address Contents 1996 1997 1998 1999 Little Endian Address Contents 1996 1997 1998 1999 Big Endian

EXPERIMENT- 4

Simulating Cache using MIPS simulator

OBJECTIVES

 To be able to understand working of cache  To learn the use of MIPS simulator

THEORY

 Refer to Chapter – 4 in order to understand cache principles  Refer to the given document “Getting Started with MIPS Simulator” to understand how to use MIPS simulator.

EXPERIMENT

1. Create a new project in MipsIt using the steps mentioned in the given document.
2. Compile code1.c and load it to the simulator
3. Open the simulator and disable both cache
4. Run the simulation and note down the execution time in Table – 1
5. Now enable the instruction cache only with default settings. Reload the code and simulate it. Note down the execution time in table – 1.
6. Next, enable the data cache only and note down the time
7. Now enable both cache (data+ instruction) and note down the time Table – 1 Scenario No Cache Instruction Cache only Data cache only Both caches Time
8. Which scenario took the least time? What is the reason?
9. Enable both cache with default values. Play the simulation. Open the Instruction Cache block by double clicking on it. What type of mapping is used by this cache? Looking at the default values, calculate the word offset bits, cache line bits and tag bits and verify it with simulator block diagram.
10. Complete the table - 2 for the same scenario Table 2 INSTRUCTION CACHE DATA CACHE

system memory. Later, if another memory location needs to use the cache line where this data is stored, it is saved ("written back") to the system memory and then the line can be used by the new address.

19. Considering the total execution time, comment which write policy is better? POST LAB Exercise: Write in detail the types of cashes, their use and different functionalities.

EXPERIMENT- 5

MEMORY ADDRESSING AND STACK

OBJECTIVES

 How to modify the memory contents.  How to use various addressing modes.  How to use the registers associated with memory.  How to use segmentation.  How use instructions like CALL, RET, PUSH and POP etc. with reference to the stack. THEORY Stack Implementation: Stack operations are facilitated by three registers:

1. The stack segment (SS) register. Stacks are implemented in memory. A system may have a number of stacks that is limited only by the maximum number of segments. A stack may be up to 4 gigabytes long, the maximum length of a segment. One stack is directly addressable at the address located by SS. This is the current stack, often referred to simply as "the" stack. SS is used automatically by the processor for all stack operations.
2. The stack pointer (SP) register points to the top of the push-down stack. It is referenced implicitly by PUSH and POP operations, subroutine calls and returns, and interrupt operations. When an item is pushed onto the stack, the processor decrements SP, then writes the item at the new position. When an item is popped off the stack, the processor copies it from the top position, then increments ESP. In other words, the stack grows down in memory toward lesser addresses.
3. The stack-frame base pointer (BP) register is the best choice of register for accessing data structures, variables and dynamically allocated work space within the stack. BP is often used to access elements on the stack relative to a fixed point on the stack rather than relative to the current top of stack. It typically identifies the base address of the current stack frame established for the current procedure. When BP is used as the base register in an offset calculation, the offset is calculated automatically in the current stack segment (i.e., the segment currently selected by SS). Because SS does not have to be explicitly specified, instruction encoding in such cases is more efficient. BP can also be used to index into segments addressable via other segment registers. [2 and 3]