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Solutions to problem set #5 of the comp 411 computer organization course, which includes circuit design problems and logic diagram analysis. Students can use this document to check their understanding of the concepts covered in the course.
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In the follows answers, the black section of the circuit is the new section, while the grey section is the section that was given in the problem.
a)
Vdd
A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0
b)
Vdd
A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0
c)
Vdd
A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0
a) When attempting to select inputs for a given circuit, it is important to eliminate any impossible combinations.
For example, in the first row, the output value of E is 0. In order to generate this value, one of the inputs must be 1 (since this value is inverted to give E). When looking at the first row, the possible selectors for the mux (X, Y, Z, and 0) are all 0, so 1 must be tied to the zeroth input on the mux.
Now consider the last row in the table. The output value for E is 1, so the mux must have selected 0 as the output. Since we already know 1, must be the zeroth input the the mux, the mux must have selected the other input to the mux and that input must have been 0. Since the X, Y, and Z values for the selector are all 1, 0 must be tied to the first mux input.
At this point, we know that the mux diagram looks like this:
X,Y,Z
However, X cannot be used as the selector, because it does not generate the correct output for the fourth row of E. Y cannot be used, since it is incorrect for the third row, and Z is incorrect for the second row. Thus, E cannot be generated with the give logic block.
After similar elimination, the only possible output is C, which is generated when I=K, J=Y, and K=Z.
b) After removing the inverter, the logic diagram appears as such:
Using similar elimination method as in a), it can be found the E is the only possible result. When using Y or Z as the selector to the mux and 0, Y, or Z as the input, many possible combinations can result in E. Here are two examples:
c) In a single level of CMOS logic, outputs of 1 can only be obtained if an input is 0 and outputs of 0 can only be obtained if an input is 1. Experimentation will show that only A can be implemented given the constraints. An example solutions is:
Vdd
Z
X Y
X
Y
Z
A
Note that an AND gate is two levels of CMOS logic: a CMOS NAND gate and a CMOS inverter.
c) Valid answers are an enumeration of all 16 gate structures, or the NAND, NOR, and INVERT structures and a comment about reducibility. A few of the more difficult enumerations follow:
B
d) Let the 4 inputs be called A, B, C, and D. 3 of the inputs (A, B, and C) will be used as the selector to the 8-input mux. The actual input to the mux must now be considered. There are four possible inputs the mux: D, D, 0, 1. These values cover all possible outputs of a 4-input boolean function. The following table describes all possible combinations.
A B C D Mux input Output
Used as mux selector
e) This is similar to the case above, except that D is no longer available. There are 3^8 selections for the 8-input mux. One of the 4 inputs must be chosen to be used as the the input value to the mux. So, there are 3^8
1
possible functions. There are a total of 2^16 4-input boolean functions. So, the upper bound is
216 , or^
38 214 functions.
