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Sequential Logic Design
Lecture
- Agenda
- VHDL : Conditional Loop
- VHDL : Attributes
- VDHL : Test Benches
- Announcements
- n/a
Conditional Loops
- Conditional Loops
- There are multiple loop structures we can use within VHDL
- Loop
- While
- For
- Loops
- "Loop" is a keyword that starts a loop
- creates an infinite loop
- useful for modeling process that go forever (i.e, clocks, time)
Conditional Loops
- While Loops
- a Boolean condition is tested at the beginning of the loop
- the loop only executes if the condition is true
ex) CLOCK_GEN : process begin clock <= '0';
while (EN = '1') clock <= not clock after 1ns; end loop;
end process CLOCK_GEN;
Conditional Loops
- For Loops
- a loop with a counter
- the loop executes the # of times in the range that is specified
syntax:
for identifier in range loop
seq-statement seq-statement
end loop;
- the "identifier" is the loop variable.
- It is implicitly declared when included in the "for" statement.
- It is automatically the same type as the "range"
- it will step through ALL values in range
Attributes
- Attributes
- ability to get more information about a signal other than its current value
- attributes allow access to the signal's history
- previous value
- time since last change
- this is how we can specify "edge triggered" events in sequential logic
- we put the attribute keyword after the signal name using the apostrophe (')
- there are many attributes, the most commonly used are:
- event
- transaction
- last_value
- last_event
Attributes
- "event" Attribute
- tells us when there was a change on the signal
- useful for edge detection
ex) "rising edge"
if (Clock'event and Clock='1')
- "transaction" Attribute
- tells us when there was an assignment is made to a signal
- the signal value does not need to change (i.e., 0 to 0)
ex) process (A'transaction)
statement if anybody ever assigns to A