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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Semester 2 Examinations 2008/
Module Title: Microprocessor Systems 2
Module Code: ELTR
School: Electrical and Electronic Engineering
Programme Title: Bachelor of Engineering in Electronic Engineering
Programme Code: CR_EELXE_7_Y
External Examiner(s): Mr D Denieffe Dr P O’Sullivan
Internal Examiner(s): Mr J O’Sullivan
Instructions: Attempt any three questions. All questions carry equal marks. Ensure you return the before-and-after sheet with your answer book.
Duration: Two hours
Sitting: Summer 2009
Requirements for this examination: N/A
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
Q1 (a) With the aid of a diagram, explain how the stack is used to facilitate subroutines in computer programs. Mention why the stack is located in the main memory of general purpose microcomputers and explain how the stack is controlled during program execution. [6 marks]
(b) It is required to generate a delay in software using a subroutine. Describe how a variable-length delay subroutine would differ from a fixed-length delay and the implications this would have when calling the subroutine from the main program. [4 marks]
(c) It is required to write a subroutine to generate a delay of 100ms as part of a control program for an industrial application. A 68000-based computer is used with a master clock frequency of 12MHz. Using the accompanying MC instruction set, write a fixed-length subroutine for this operation. Show and explain all calculations when determining the length of the delay. You may find the following information useful: Execution times: SUB.L = 16 mpu cycles, BNE = 10 mpu cycles. [8 marks]
(d) Show how this subroutine would be called from the main program. [2 marks]
Q2 (a) In the main memory of a 68000-based computer, briefly describe the function of the following control lines and identify and explain how one on them is used for asynchronous bus control. AS UDS LDS R / W DTACK [5 marks]
(b) Draw a detailed circuit diagram to show how two 32kByte byte-organised chips would be connected in a 68000-based computer to implement a 64kByte block of fast RAM, paying particular attention to all of the above control lines. [10 marks]
(c) With the aid of an addressing map and decoder circuit, show how the block of RAM could be positioned in memory with a base address of $C60000. [5 marks]
Q3 (a) In relation to serial datacommunications, draw a timing diagram and explain the principle of asynchronous data transfer. Explain how the receiving computer is able to maintain synchronism with the transmitting computer for correct reception of data. [6 marks]
(b) What is meant by a UART chip and explain briefly its role in serial datacommunications. Draw a block diagram showing the internal structure of this device. [6 marks]
(c) Complete the before-and-after table attached to this paper. [8 marks]
CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Semester 2 Examinations 2008/
Module Title: Microprocessor Systems 2
BEFORE-AND-AFTER SHEET
Question 3(c)
Name: _______________________ Return with your answer book
X N Z V C
0 1 0 1 0
Registers before Flags before Instruction Registers after Flags after
D0: 87654321
D1: 12345678
D0: 19A42B6A
D1: B72D
D0: 7125BA9C
1 0 0 1 0 X N Z V C
X N Z V C 1 0 0 1 0
MOVE.L D0,D
CMP.B D1,D
OR.B #$F0,D
D0: D1:
X N Z V C
D0: D1:
X N Z V C
D0: X N^ Z^ V^ C
D0: 41D60783 X N^ Z^ V^ C 0 1 0 1 0
LSL.B #1,D0 D0: X N^ Z^ V^ C
