EXPERIMENT
5
CONTROL UNIT DESIGN
VERSION S07
In this experiment, you will design a finite state machine controller, and integrate it into a design using the logic
functions you have created previsously. After performing this experiment, you should be able to:
1) Design a one flip-flop per state control unit to implement a given algorithmic state machine (ASM) diagram,
2) Use simulation to test the operation of your controller independent of other circuit modules, and
3) Integrate your controller into a fully functional design, performing testing and debugging as needed to ensure
proper operation.
5-1 PRELAB
In this prelab, you will be designing a state machine to act as a control unit for a frequency counter. Perhaps the
most obvious way to implement a frequency counter is to simply count signal changes (C = number of 0Æ1 edges)
for a fixed period of time (T), then the signal frequency can be calculated as FSIGNAL = C / T. We have already
created all of the major building blocks (i.e. BCD counters and decoders, divide-by-N counter) that we will need for
this in previous labs, now we need to design and implement a state machine to control the operation of those blocks.
In particular, we will be implementing the controller as a state machine using the one FF per state method (also
referred to as a one-hot controller); as preparation for this prelab and lab you should first review Mano and Kime [1]
pages 406-410.
Fewer step-by-step instructions are provided for tasks you have completed in earlier labs, as you should be
becoming fairly accomplished in using the Altera Quartus II toolset. The issues of tool complexity and the learning
curves associated with the tools are something that you will deal with routinely as a design engineer. Since we will
often be designing with the most recent technology, the tool sets are often immature and less than robust. So, we
will need to be able to fight our way through the various errors and omissions (and our own self-inflicted troubles)
that we will discover in our hardware, software and documentation in order to bring our design to fruition. If you
need to, review the previous labs as a reminder of how to accomplish tasks that you encounter in this lab.
OVERVIEW
This lab will build on the functional blocks that you created in experiments 3 and 4, and we will add a finite state
machine (FSM) to create a useful machine. We will be developing a frequency counter based on the block diagram
shown below in Figure 1. The blocks that are highlighted in thicker blue lines are logic that you have already
designed or that will be provided for you. All of the items in the thicker blue blocks are contained in a schematic
sheet FREQCNT.BDF that will be provided for you to use. The contents of FREQCNT.BDF are shown below in
Figure 2. Although the logic is largely complete, you will still need to add synchronizing flip-flops to the external
inputs, add circuitry to generate a pulse on input transitions, and make the various connections to your controller.
You will design your controller on a separate sheet (CONTROL.BDF), then create a symbol for it, add that symbol
FREQCNT.BDF, and make the necessary connections.
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