Controller Design Exceptions - Computer Organization - Lecture Slides, Slides of Computer Science

Download Controller Design Exceptions - Computer Organization - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

CS 152: Computer Architecture

and Engineering

Lecture 11

Multicycle Controller Design

Exceptions

The Big Picture: Where are We Now?

 The Five Classic Components of a Computer

 Today’s Topics:

• Microprogramed control
• Microprogram it yourself
• Exceptions
• Intro to Pipelining (if time permits)

Control

Datapath

Memory

Processor Input

Output

Recap: Finite State Machine (FSM) Spec

IR <= MEM[PC] PC <= PC + 4

R-type ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW

“instruction fetch”

“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010

If A = B then PC <= ALUout

ALUout <= PC +SX

Execute

Memory

Write-back

Recap: Specific Sequencer from last lecture

Sequencer-based control unit from last lecture

• Called “microPC” or “μPC” vs. state register

Control Value Effect

00 Next μaddress = 0 01 Next μaddress = dispatch ROM 10 Next μaddress = μaddress + 1

ROM:

Opcode

microPC

μAddress

Select

Logic

Adder

ROM

Mux

R-type 000000 0100 BEQ 000100 0011 ori 001101 0110 LW 100011 1000 SW 101011 1011

Microprogram It Yourself!

Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write Sequencing Fetch: Add PC 4 Read PC IR ALU Seq Add PC Extshft Dispatch

Rtype: Func rs rt Seq rd ALU Fetch

Ori: Or rs Extend0 Seq rt ALU Fetch

Lw: Add rs Extend Seq Read ALU Seq rt MEM Fetch

Sw: Add rs Extend Seq Write ALU Fetch

Beq: Subt. rs rt ALUoutCond. Fetch

Test Benches

 Idea: wrap testing infrastructure around devices under

test (DUT)

 Include test vectors that are supposed to detect errors in

implementation. Even strange ones…

 Can (and probably should in later labs) include assert

statements to check for “things that should never happen”

Test Bench

Device Under Test

Inline vectors Assert Statements File IO (for patterns or output diagnostics)

Inline Monitor

Output in readable format (disassembly) Assert Statements

Complete Top-Level Design

Two Types of Exceptions: Interrupts and Traps

 Interrupts

• Caused by external events:
  • Network, Keyboard, Disk I/O, Timer
• Asynchronous to program execution
  • Most interrupts can be disabled for brief periods of time
  • Some (like “Power Failing”) are non-maskable (NMI)
• May be handled between instructions
• Simply suspend and resume user program

 Traps

• Caused by internal events
  • Exceptional conditions (overflow)
  • Errors (parity)
  • Faults (non-resident page)
• Synchronous to program execution
• Condition must be remedied by the handler
• Instruction may be retried or simulated and program continued or program may be aborted Docsity.com

Traps and Interrupts

 Exception means any unexpected change in control flow, without distinguishing internal or external;

Type of event From where? terminology

I/O device request External Interrupt Invoke OS from usr program Internal Trap Arithmetic overflow Internal Trap Using undefined instruction Internal Trap Hardware malfunctions Either Trap or Interrupt

Precise Interrupts

 Precise ⇒ state of the machine is preserved as if

program executed up to the offending instruction

• All previous instructions completed
• Offending instruction and all following instructions act as if they have not even started
• Same system code will work on different implementations
• Difficult in the presence of pipelining, out-of-order execution, ...
• MIPS takes this position

 Imprecise ⇒ system software has to figure out what is

where and put it all back together

 Performance goals often lead designers to not implement

precise interrupts

• System software developers, user, markets etc. usually wish they had not done this

 Modern techniques for out-of-order execution and

branch prediction help implement precise interrupts

Big Picture: User / System modes

 By providing two modes of execution (user/system) it is

possible for the computer to manage itself

• OS is a special program that runs in the privileged mode and has access to all of the resources of the computer
• Presents “virtual resources” to each user that are more convenient that the physical resources - files vs. disk sectors - virtual memory vs physical memory
• Protects each user program from others
• Protects system from malicious users.
• OS is assumed to “know best”, and is trusted code, so enter system mode on exception.

 Exceptions allow the system to taken action in response

to events that occur while user program is executing:

• Might provide supplemental behavior (dealing with denormal floating-point numbers for instance).
• “Unimplemented instruction” used to emulate instructions that were not included in hardware

Saving State

 Push it onto the stack

• 68k, 80x

 Shadow Registers

• M88k
• Save state in a shadow of the internal pipeline registers

 Save it in special registers

• MIPS EPC, BadVaddr, Status, Cause

Additions to MIPS ISA to Support Exceptions?

 Exception state is kept in “coprocessor 0”.

• Use mfc0 read contents of these registers
• Every register is 32 bits, but may be only partially defined

BadVAddr (register 8)

• register contains memory address at which memory reference occurred Status (register 12)
• interrupt mask and enable bits Cause (register 13)
• the cause of the exception
• Bits 5 to 2 of this register encodes the exception type (e.g undefined instruction=10 and arithmetic overflow=12) EPC (register 14)
• address of the affected instruction (register 14 of coprocessor 0).

 Control signals to write BadVAddr, Status, Cause, and EPC  Be able to write exception address into PC (8000 0080 (^) hex )  May have to undo PC = PC + 4, since want EPC to point to offending instruction (not its successor): PC = PC - 4

Details of Cause Register

 Pending interrupt 5 hardware levels: bit set if interrupt occurs but not yet serviced

• handles cases when more than one interrupt occurs at same time, or while records interrupt requests when interrupts disabled

 Exception Code encodes reasons for interrupt

• 0 (INT) => external interrupt
• 4 (ADDRL) => address error exception (load or instr fetch)
• 5 (ADDRS) => address error exception (store)
• 6 (IBUS) => bus error on instruction fetch
• 7 (DBUS) => bus error on data fetch
• 8 (Syscall) => Syscall exception
• 9 (BKPT) => Breakpoint exception
• 10 (RI) => Reserved Instruction exception
• 12 (OVF) => Arithmetic overflow exception

Status

Pending

Code

Example: How Control Handles Traps in our FSD

 Undefined Instruction–detected when no next state is

defined from state 1 for the op value.

• Handle this by defining the next state value for all op values other than lw, sw, 0 (R-type), jmp, beq, and ori as new state 12.
• Shown symbolically using “other” to indicate that the op field does not match any of the opcodes that label arcs out of state 1.

 Arithmetic overflow–detected on ALU ops like signed add

• Used to save PC and enter exception handler

 External Interrupt – flagged by asserted interrupt line

• Again, must save PC and enter exception handler

 Note: Challenge in designing control of a real machine is

to handle different interactions between instructions

and other exceptions-causing events such that control

logic remains small and fast.

• Complex interactions makes the control unit the most challenging aspect of hardware design