Computer Architecture & Assembly Language
Programming
Course Code: CS401
Virtual University of Pakistan 96
divide by zero interrupt. A list of all reserved interrupts is given later. Such
interrupts are programmed in the hardware to generate the designated
interrupt when the specified condition arises. The remaining interrupts are
provided by the processor for our use. Some of these were reserved by the
IBM PC designers to interface user programs with system software like DOS
and BIOS. This was the logical choice for them as interrupts provided a very
flexible architecture. The remaining interrupts are totally free for use in user
software.
The correlation process from the interrupt number to the interrupt handler
uses a table called interrupt vector table. Its location is fixed to physical
memory address zero. Each entry of the table is four bytes long containing
the segment and offset of the interrupt routine for the corresponding
interrupt number. The first two bytes in the entry contain the offset and the
next two bytes contain the segment. The little endian rule of putting the more
significant part (segment) at a higher address is seen here as well.
Mathematically offset of the interrupt n will be at nx4 while the segment will
be at nx4+2. One entry in this table is called a vector. If the vector is changed
for interrupt 0 then INT 0 will take execution to the new handler whose
address is now placed at those four bytes. INT 1 vector occupies location 4,
5, 6, and 7 and similarly vector for INT 2 occupies locations 8, 9, 10, and 11.
As the table is located in RAM it can be changed anytime. Immediately after
changing it the interrupt mapping is changed and now the interrupt will
result in execution of the new routine. This indirection gives the mechanism
extreme flexibility.
The operation of interrupt is same whether it is the result of an INT
instruction (software interrupt) or it is generated by an external hardware
which passes the interrupt number by a different mechanism. The currently
executing instruction is completed, the current value of FLAGS is pushed on
the stack, then the current code segment is pushed, then the offset of the
next instruction is pushed. After this it automatically clears the trap flag and
the interrupt flag to disallow further interrupts until the current routine
finishes. After this it loads the word at nx4 in IP and the word at nx4+2 in CS
if interrupt n was generated. As soon as these values are loaded in CS and IP
execution goes to the start of the interrupt handler. When the handler
finishes its work it uses the IRET instruction to return to the caller. IRET
pops IP, then CS, and then FLAGS. The original value of IF and TF is
restored which re-enables further interrupts. IF and TF will be discussed in
detail in the discussion of real time interrupts. We have discussed three
things till now.
1. The INT and IRET instruction format and syntax
2. The formation of IVT (interrupt vector table)
3. Operation of the processor when an interrupt in generated
Just as discussed in the subroutines chapter, the processor will not match
interrupt calls to interrupt returns. If a RETF is used in the end of an ISR the
processor will still return to the caller but the FLAGS will remain on the
stack which will destroy the expectations of the caller with the stack. If we
