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In this document, students are introduced to the root locus controller design methodology using the Matlab 'sisotool' toolbox. The goal is to design various controller structures, including P, I, PD, PI, and PID controllers, to meet specified performance constraints such as settling time, percent overshoot, and damping ratio. Students will explore the root locus plot, add poles and zeros, and adjust controller gains to achieve the desired performance.
Typology: Essays (high school)
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In this lab you will explore the use of the root locus controller design methodology. The root locus indicates the achievable closed‐loop pole locations of a system as a parameter (usually the controller gain) varies from zero to infinity. For a given plant it may or may not be possible to implement a simple proportional controller (i.e., select a gain that specifies closed‐loop pole locations along the root locus) to achieve the specified performance constraints. In fact, in most cases it will not be possible. When this occurs, it is the control engineer’s job to select a controller structure (a gain and numbers of poles and zeros of a controller transfer function) and the respective controller parameters (values for the gain and poles and zeros) to change the shape of the root locus so that for some values of the controller gain, the dominant second order closed‐loop poles lie within the performance region. In this lab we are investigating several controller structures on individual plants and comparing the design process and performance. We will be using the Matlab ‘sisotool’ toolbox to complete the root locus designs.
At the conclusion of this laboratory experience, students should be able to:
A completed worksheet including the following:
For this lab, we will assume a unity feedback controller of the form shown in Figure 1, where ሻݏሺܥ is the controller transfer function and ܲ ሻݏሺ^ is the plant transfer function.
Figure 1 – Generic Unity Feedback Control System.
Controller^ Plant
Note, in controller design there are multiple possible solutions, some better than others. It is possible to have multiple designs that satisfy the given performance constraints, but practical implementation issues and cost could be prohibitive for some designs. As a general rule, it is a good idea to keep your controller as simple as possible while meeting the prescribed performance criteria. In this lab we will be investigating several controller structures on individual plants and comparing the design process and performance. The common controller structures we will be using in this lab are listed in Table 1 along with their respective transfer functions.
Table 1 – Common Controller Types Controller Type Controller Structure
Proportional (P) ݇ൌ ሻݏሺܥ^
Integral (I) (^) ݇ൌ ሻݏሺܥ (^) ݏ
Proportional + Integral (PI) (^) ݇ൌ ሻݏሺܥ (^) ݇ ݏ ݇ൌ
Lag Controller ܥሺݏሻ ൌ ܭሺ ݏ ሻ^ · ሺ ݏ ݖሻ where | |ݖ ||
Proportional + Derivative (PD) ݇ൌ ሻݏሺܥ^ ݇^ ௗ · ݇ൌ ݏ^ ሺ ݏ ݖሻ
Lead Controller ݇ൌ ሻݏሺܥ·^
ሺ ݏ ሻ where | | |ݖ|
Proportional + Integral + Derivative (PID) (Real Zeros) ݇ൌ ሻݏሺܥ^ ^ ݇^
ݏ݇^ ௗ^ ݇ൌ ݏ
Proportional + Integral + Derivative (PID) (Complex Conjugate Zeros) ݇ൌ ሻݏሺܥ^ ^ ݇^
ݏ݇^ ௗ^ ݇ൌ ݏ
Note that the I, PI, and PID controller’s will produce a position error (݁ (^) ) of zero as long as the plant does not contain a zero at the origin, which would cancel the controllers pole at the origin.
D. Entering the Compensator (Controller)
E. Adding Design Constraints
F. Printing/Saving the Figures To save a figure ‘sisotool’ created during your session, click File Æ Print to Figure. This opens a figure window and puts the current figure there.
G. Odds and Ends
Use the plant given in (3) for this section of the lab.
ܲ ሺݏሻ ൌ (^) ௦ మ (^) ାଵଵ௦ାଷଷ ൌ (^) ሺ௦ାହሻሺ௦ାሻଷ (3)
This is a second order system with two real poles located at ‐ 5 and ‐6. Our goal is to speed up the closed‐ loop system response so that the two‐percent settling time is less than 1 second, produce a position error of 0.1 or less, and keep percent overshoot less than 10%. To keep things reasonable, keep the gain, ݇ , less than 10 for all designs.
1. Entering the Constraints Enter the percent overshoot and settling time constraints in ‘sisotool’. Remember that these constraints are based on a second order system step response and for higher order systems are predicated by the assumption of second order dominance of the closed‐loop system poles. Therefore, these design constraints are guidelines and you may have to refine your design to stay further inside these constraints to meet the performance specifications. 2. Proportional (P) Control Determine the root locus for this system with proportional control. (When you enter the plant transfer function in ‘sisotool’, this is the default root locus plot. At this point the controller is specified as ܥሺݏሻ ൌ 1.
Look at the step response as the gain increases. You should notice a few things:
second, and a position error of less than 0.01. (Remember to keep ݇ ൏ 10 .) Save the step response and control effort figure and the controller that produced it. d) Now let’s make a PID controller with real zeros at ‐ 7 and ‐8. Determine the root locus for this system. Find a value of ݇ on this root locus so that percent overshoot is less than 2% and the settling time is less than 1 second. (Remember to keep ݇ ൏ 10 .) Save the step response and control effort figure and the controller that produced it.
Use the plant given in (4) for this section of the lab.
ܲ ሺݏሻ ൌ଼ (^) .ଵସ௦ మ.ଽ (^) ା.ଵସହହ௦ାଵ (4)
This is a model obtained from one of the mass‐spring‐damper systems in the controls lab.
Performance Constraints
Controller Parameter Constraints
Meet these design constraints by implementing the following controller structures
For each one of these controller designs, you need to include your plot of the step response, your controller parameters, and the steady state error.