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TECHNICAL REPORT

DATA COMMUNICATION ERROR

DETECTION USING CYCLIC

REDUNDANCY CHECK

Author: Supervisor:

4 Contents

Abstract

Environmental interference and physical defects in the communication medium can cause random bit errors during data transmission. Error coding is a method of de- tecting and correcting these errors to ensure information is transferred intact from its source to its destination. There are many methods which have been developed to detect errors, applied at different levels of the sevenlayer model. Of course, no method can detect all errors, but a number of methods in use today are amazingly effective. The one we will discuss here is the famous CRC coding form. In this project, we provides an overview and principle of CRC. Emphasis is placed on the mathematical background of CRC algorithm and the implementation of the CRC algorithm by method of hardware as well as software. It is proved that the implementation method present has high practical value.

Chapter 1

ERROR IN COMMUNICATION

1.1 Introduction to error in communication

Environmental interference and physical defects in the communication medium can cause random bit errors during data transmission. Error coding is a method of de- tecting and correcting these errors to ensure information is transferred intact from its source to its destination. Error coding is used for fault tolerant computing in com- puter memory, magnetic and optical data storage media, satellite and deep space communications, network communications, cellular telephone networks, and al- most any other form of digital data communication. Error coding uses mathematical formulas to encode data bits at the source into longer bit words for transmission. The "code word" can then be decoded at the destination to retrieve the information. The extra bits in the code word provide redundancy that, according to the coding scheme used, will allow the destination to use the decoding process to determine if the communication medium introduced errors and in some cases correct them so that the data need not be retransmitted. Different error coding schemes are chosen depending on the types of errors expected, the communication medium’s expected error rate, and whether or not data retransmission is possible. Faster processors and better communications technology make more complex coding schemes, with better error detecting and correcting capabilities, possible for smaller embedded systems, allowing for more robust communications. However, tradeoffs between bandwidth and coding overhead, coding complexity and allowable coding delay between trans- missions, must be considered for each application. Even if we know what type of er- rors can occur, we can’t simple recognize them. We can do this simply by comparing this copy received with another copy of intended transmission. In this mechanism the source data block is send twice. The receiver compares them with the help of a comparator and if those two blocks differ, a request for re-transmission is made. To achieve forward error correction, three sets of the same data block are sent and majority decision selects the correct block. These methods are very inefficient and increase the traffic two or three times. Fortunately, there are more efficient error de- tection and correction codes. There are two basic strategies for dealing with errors. One way is to include enough redundant information (extra bits are introduced into the data stream at the transmitter on a regular and logical basis) along with each block of data sent to enable the receiver to deduce what the transmitted character must have been. The other way is to include only enough redundancy to allow the receiver to deduce that error has occurred, but not which error has occurred and the receiver asks for a retransmission. The former strategy uses Error-Correcting Codes and latter uses Error-detecting Codes. To understand how errors can be handled, it is necessary to look closely at what error really is. Normally, a frame consists of m- data bits (i.e., message bits) and r-redundant bits (or check bits). Let the total number of bits be n (m + r). An n-bit unit containing data and check-bits is often referred to

1.3. Error Detecting Codes 7

FIGURE 1.2: Burst errors

1.3 Error Detecting Codes

Basic approach used for error detection is the use of redundancy, where additional bits are added to facilitate detection and correction of errors. Popular techniques are:

• Simple Parity check
• Two-dimensional Parity check
• Checksum
• Cyclic redundancy check

1.3.1 Simple Parity Checking or One-dimension Parity Check

The most common and least expensive mechanism for error- detection is the sim- ple parity check. In this technique, a redundant bit called parity bit, is appended to every data unit so that the number of 1s in the unit (including the parity becomes even). Blocks of data from the source are subjected to a check bit or Parity bit gen- erator form, where a parity of 1 is added to the block if it contains an odd number of 1’s (ON bits) and 0 is added if it contains an even number of 1’s. At the receiving end the parity bit is computed from the received data bits and compared with the received parity bit, as shown in Fig.1.3. This scheme makes the total number of 1’s even, that is why it is called even parity checking. Considering a 4-bit word, differ- ent combinations of the data words and the corresponding code words are given in Fig 1.4. Note that for the sake of simplicity, we are discussing here the even-parity check- ing, where the number of 1’s should be an even number. It is also possible to use odd-parity checking, where the number of 1’s should be odd. Performance An ob- servation of the table reveals that to move from one code word to another, at least two data bits should be changed. Hence these set of code words are said to have a minimum distance (hamming distance) of 2, which means that a receiver that has knowledge of the code word set can detect all single bit errors in each code word. However, if two errors occur in the code word, it becomes another valid member of the set and the decoder will see only another valid code word and know nothing of the error. Thus, errors in more than one bit cannot be detected. In fact, it can be shown that a single parity check code can detect only odd number of errors in a code word.

8 Chapter 1. ERROR IN COMMUNICATION

FIGURE 1.3: Even-parity checking scheme

FIGURE 1.4: Possible 4-bit data words and corresponding code words

10 Chapter 1. ERROR IN COMMUNICATION

FIGURE 1.6: (a) Sender’s end for the calculation of the checksum, (b) Receiving end for checking the checksum

Chapter 2

CYCLIC REDUNDANCY CHECKS

(CRC)

2.1 Introduction

A cyclic redundancy check (CRC) is an error-detecting code commonly used in digi- tal networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short check value attached, based on the remain- der of a polynomial division of their contents; on retrieval the calculation is repeated, and corrective action can be taken against presumed data corruption if the check val- ues do not match. CRCs are so called because the check (data verification) value is a redundancy (it adds no information to the message) and the algorithm is based on cyclic codes. CRCs are popular because they are simple to implement in binary hardware, easy to analyze mathematically, and particularly good at detecting com- mon errors caused by noise in transmission channels. Because the check value has a fixed length, the function that generates it is occasionally used as a hash function. The CRC was invented by W. Wesley Peterson in 1961; the 32-bit polynomial used in the CRC function of Ethernet and many other standards is the work of several researchers and was published during 1975. Cyclic redundancy codes (also known sometimes as cyclic redundancy checks) have a long history of use for error detection in computing. A treatment more ac- cessible to non-specialists can be found in [Wells99]. A CRC can be thought of as a (non-secure) digest function for a data word that can be used to detect data cor- ruption. Mathematically, a CRC can be described as treating a binary data word as a polynomial over GF(2) (i.e., with each polynomial coefficient being zero or one) and performing polynomial division by a generator polynomial G(x). The genera- tor polynomial will be called a CRC polynomial for short. (CRC polynomials are also known as feedback polynomials, in reference to the feedback taps of hardware- based shift register implementations.) The remainder of that division operation pro- vides an error detection value that is sent as a Frame Check Sequence (FCS) within a network message or stored as a data integrity check. Whether implemented in hardware or software, the CRC computation takes the form of a bitwise convolution of a data word against a binary version of the CRC polynomial. Error detection is performed by comparing an FCS computed on a piece of retrieved or received data against the FCS value originally computed and either sent or stored with the origi- nal data. An error is declared to have occurred if the stored FCS and computed FCS values are not equal. However, as with all digital signature schemes, there is a small, but finite, probability that a data corruption that inverts a sufficient number of bits in just the right pattern will occur and lead to an undetectable error. The minimum number of bit inversions required to achieve such undetected errors (i.e., the HD

2.3. Performance of CRC 13

process without any carry over, which is just the Exclusive-OR operation. Consider the case where k =1101. Hence, we have to divide 1101000 (i.e. k appended by 3 zeros) by 1011, which produces the remainder r = 001, so that the bit frame (k+r) = 1101001 is actually being transmitted through the communication channel. At the receiving end, if the received number, i.e., 1101001 is divided by the same generator polynomial 1011 to get the remainder as 000, it can be assumed that the data is free of errors.

FIGURE 2.2: Cyclic Redundancy Checks (CRC)

The transmitter can generate the CRC by using a feedback shift register circuit. The same circuit can also be used at the receiving end to check whether any error has occurred. All the values can be expressed as polynomials of a dummy variable X. For example, for P = 11001 the corresponding polynomial is X^4 + X^3 + 1. A polynomial is selected to have at least the following properties:

• It should not be divisible by X.
• It should not be divisible by (X+1).

The first condition guarantees that all burst errors of a length equal to the degree of polynomial are detected. The second condition guarantees that all burst errors affecting an odd number of bits are detected. CRC process can be expressed as XnM(X)/P(X) = Q(X) + R(X)/P(X) Commonly used divisor polynomials are:

• CRC-16 = X16 + X15 + X2 + 1
• CRC-CCITT = X16 + X12 + X5 + 1
• CRC-32 = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X
  • X2 + 1

2.3 Performance of CRC

CRC is a very effective error detection technique. If the divisor is chosen according to the previously mentioned rules, its performance can be summarized as follows:

• CRC can detect all single-bit errors

14 Chapter 2. CYCLIC REDUNDANCY CHECKS (CRC)

• CRC can detect all double-bit errors (three 1’s)
• CRC can detect any odd number of errors (X+1)
• CRC can detect all burst errors of less than the degree of the polynomial
• CRC detects most of the larger burst errors with a high probability

For example, CRC-12 detects 99.97% of errors with a length 12 or more

16 Chapter 2. CYCLIC REDUNDANCY CHECKS (CRC)

Reference

1. A. Perez, “Byte-wise CRC Calculations”, IEEE Micro, Vol. 3, No. 3, June 1983, pp. 40-
2. G. Albertango and R. Sisto, “Parallel CRC Generation”, IEEE Micro, Vol. 10, No. 5, October 1990, pp. 63-
3. T. V. Ramabadran and S. S. Gaitonde, “A Tutorial on CRC Computations”, IEEE Micro, Vol.8, No. 4, August 1988, pp. 62-
4. R. F. Hobson and K. L, Cheung, “A High-Performance CMOS 32-Bit Parallel CRC Engine”, IEEE Journal Solid State Circuits, Vol. 34, No. 2, Feb 1999
5. T. B. Pei and C. Zukowski, “High-speed parallel CRC cicuits in VLSI”, IEEE Transaction Communication, Vol. 40, No. 4, pp. 653-657, 1992
6. Dost Muhammad Saqib Bhatti, Saleem Ahmed, Nasir Saeed, Bushra Shaikh, "Efficient error detection in soft data fusion for cooperative spectrum sensing", AEU - International Journal of Electronics and Communications, vol. 88, pp. 141, 2018.
7. Swati Chaturvedi, Sukrut Pasumarthi, Nan Wang, "Implementation and Per- formance Analysis of Two Error Detection and Correction Techniques", In- ternational Journal of Interdisciplinary Telecommunications and Networking, vol. 10, pp. 36, 2018.
8. Sang Sheng-Ju, "Implementation of Cyclic Redundancy Check in Data Com- munication", 2015 International Conference on Computational Intelligence and Communication Networks (CICN, 12-14 Dec. 2015