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Computer Architecture and Machine Language: An Introduction - Prof. Lonnie E. Cheney, Study notes of Computer Science

Christopher Newport University (CNU)Computer Science
Prof. Lonnie E. Cheney

An introduction to computer architecture, machine language, program execution, arithmetic/logic instructions, communication with other devices, and other architectures. It covers topics such as the von neumann architecture, registers, machine instructions, data transfer, arithmetic/logic instructions, control/branching, and peripherals.

Typology: Study notes

Pre 2010

Uploaded on 08/18/2009

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Introduction to Computer Science
Data Manipulation
Dr. Lonnie Cheney
Slide 2
Outline
๎˜Computer Architecture
๎˜Machine Language
๎˜Program Execution
๎˜Arithmetic/Logic Instructions
๎˜Communication with other Devices
๎˜Other Architectures
Slide 3
Outline
๎˜Computer Architecture
๎˜Machine Language
๎˜Program Execution
๎˜Arithmetic/Logic Instructions
๎˜Communication with other Devices
๎˜Other Architectures
Slide 4
Computer Architecture
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Download Computer Architecture and Machine Language: An Introduction - Prof. Lonnie E. Cheney and more Study notes Computer Science in PDF only on Docsity!

Introduction to Computer Science

Data Manipulation

Dr. Lonnie Cheney

Slide 2

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 3

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 4

Computer Architecture

Slide 5

von Neumann Architecture

  • data and instructions kept in memory
  • CPU fetches and executes instructions
  • CPU connected to memory via data and address bus
  • one instruction executed at a time

Slide 6

Registers

  • special processor memory for temporary storage of results
  • very fast access time compared to primary memory
  • example: add two numbers from memory
    • one register holds first number
    • another holds second number
    • third holds the answer
  • special registers: program counter, instruction

Slide 7

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 8

Machine Instructions

  • CPU has several circuits which perform different functions
  • identify each function (command, instruction) with a unique bit pattern, just as ASCII code represents each character with a unique bit pattern
  • types of instructions: data transfer arithmetic/logic control/branching

Slide 13

Example of control flow

  • sample program to add two numbers
    1. load register one with first number from memory
    2. load register two with second number from memory
    3. add contents of registers one and two, leave answerin register 3
    4. if contents of register 3 are negative, jump to step 6
    5. store contents of register 3 to a location in memory
    6. stop
  • identify the data transfer, arithmetic/logic, and control instructions above

Slide 14

How it works inside the PC

load R1 from M load R2 from M add R1, R2  R if neg jmp M store R3 to M stop 10 20

CPU MEMORY

Slide 15

Stored program ...

  • instructions can be represented by bit patterns
  • bit patterns can be stored in memory
  • instead of building in programs in CPU, store programs in memory
  • CPU then interprets patterns as instructions or data

Slide 16

Opcodes & Operands

  • opcode: bit pattern representing instruction
  • operand: bit pattern representing object of instruction
  • example: LOAD REG1 ADDR  instruction = load, objects of instruction = reg1 and addr
  • complete instruction = opcode and operand

Slide 17

Opcode examples

  • the LOAD instruction has opcode 0001 (appendix C)
  • computer will load a specified register with contents of some memory location
  • need to indicate which register to load, and what memory location to access
  • use more bits after the 0001 to indicate this info

Slide 18

CISC vs. RISC

  • CISC: Complex Instruction Set Computer many powerful instructions, ex: expon, sqrt more CPU silicon devoted to instruction circuits programs are shorter
  • RISC: Reduced Instruction Set Computer few simple instructions, ex: add, mov more registers on CPU, rather than instruction circuits programs are longer

Slide 19

A simple machine

  • CPU has 16 registers, each 8 bit wide
  • registers identified as 0 to F
  • memory has 256 cells (words), each 8 bits wide
  • memory address ranges from 00 to FF
  • each instruction is 16 bits (two words) with first 4 bits the opcode and remaining 12 the operand

Slide 20

Architecture of simple machine

Slide 25

And this?

Slide 26

And this?

Slide 27

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 28

Program Execution

  • Fetch-decode-execute cycle
  • Program counter (PC) register points to next instruction in memory to execute
  • Instruction register holds instruction to be decoded and executed

Slide 29

Fetch-decode-execute cycle

  • set the PC to the location of the first instruction
  • copy instruction from memory to the instruction register. PC register states which memory location to copy from.
  • increment PC to point to next instruction in memory
  • decode and execute bit pattern in instruction register
  • when instruction is done, start from step 2 above

Slide 30

Fetch-decode-execute cycle

Slide 31

Example

Slide 32

Example

Slide 37

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 38

Peripherals

  • communication with external devices via controllers
  • example: printers, disk drivers, monitors, modems
  • different devices have different processing speeds
  • need to synchronize communications
  • should not keep CPU waiting for I/O to finish
  • serial/parallel communication

Slide 39

Peripherals

Slide 40

Peripherals

source: www.howstuffworks.com

Slide 41

Memory Mapped I/O

  • replace a memory cell with a port, send data to device by storing data to that memory cell
  • no need for special I/O instructions
  • lose a memory cell for every port

Slide 42

Direct Memory Access (DMA)

  • simple specialized computer to control peripherals (controller, channel)
  • share memory with CPU
  • Basic method (output)
    • CPU stores data in memory at given location
    • CPU signals controller to start I/O
    • Controller reads memory at the given location
    • Controller performs I/O
  • CPU doesnโ€™t wait for I/O
  • Specialized I/O instructions required

Slide 43

**-

-**

MEMORY
CPU

controller

printer

CPU stores data ...

Slide 44

CPU signals controller ...

**-

-**

MEMORY
CPU

controller

printer

Slide 49

Outline

 Computer Architecture

 Machine Language

 Program Execution

 Arithmetic/Logic Instructions

 Communication with other Devices

 Other Architectures

Slide 50

Speed

  • clock allows synchronization of processes
  • directly affects rate of fetch-execute cycle
  • word size
  • data bus width
  • von Neumann Bottleneck
  • benchmarks

Slide 51

Speed of Light Limit

  • 300,000 km/sec = 30 cm/nanosecond
  • 1 ns = 10-9^ sec
  • electrons cannot travel faster than this
  • directly affects rate of fetch-execute cycle
  • electrons must travel through the address and data busses, memory circuits, etc.
  • Throughput: measure of work done Execution speed: time to execute an instruction

Slide 52

Pipeline

  • machine cycle has 3 phases: fetch-decode-execute
  • consider this as a โ€œpipeโ€ with 3 segments
  • each segment can hold one instruction
  • when pipe is full, there are 3 instructions in various phases of execution
  • also known as pre-fetch

Slide 53

Pipeline Illustration

11B
10AF
10AF^ MEM
11B0 10AF
5001 11B0 10AF

TIME fetch decode exec.

5001 11B

Slide 54

Pipeline vs. non-pipeline

non-pipeline pipeline

done >

< done

Slide 55

Multiprocessing

  • use more than one processor (parallel)
  • shared memory
  • inter-processor communication
  • Single Instruction, Multiple Data
  • Multiple Instruction, Multiple Data
  • Distributed processing
  • Neural Nets