Datapath Elements: Register Files, Adders/Subtractors, and Logical Units, Exams of Electrical and Electronics Engineering

A chapter extract from a microprocessor design textbook, discussing various datapath elements such as register files, adders/subtractors, and logical units. It covers topics like register layout, write and read decoders, 32-bit register files, adders/subtractors with carry-in and carry-out signals, and logical functions. The text also mentions the implementation of logical units using bit slices and the introduction of shift units.

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R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.
CHAPTER XI-1
DATAPATH ELEMENTS
•CHAPTER XI
CHAPTER XI
DATAPATH ELEMENTS
READ DATAPATH ELEMENTS FREE-DOC ON COURSE WEBPAGE
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Download Datapath Elements: Register Files, Adders/Subtractors, and Logical Units and more Exams Electrical and Electronics Engineering in PDF only on Docsity!

INTRO. TO COMP. ENG.

CHAPTER XI-

DATAPATH ELEMENTS

•CHAPTER XI

CHAPTER XI

DATAPATH ELEMENTS

READ DATAPATH ELEMENTS FREE-DOC ON COURSE WEBPAGE

INTRO. TO COMP. ENG.

CHAPTER XI-

DATAPATH ELEMENTS

INTRODUCTION

DATAPATH ELEMENTS

-

DATAPATH ELEMENTS

-INTRODUCTION

So far we have discussed many small components and buildingblocks.

One final step in our building blocks before we can start to piecetogether a microprocessor is various datapath elements. •

We have already discussed portions of these datapath elements in terms of other components and building blocks.

We will now consider some of these components and building blocks in ways that will make the design of a microprocessor a little easier in thenext chapter.

INTRO. TO COMP. ENG.

CHAPTER XI-

REGISTER FILES

WRITE DECODER

DATAPATH ELEMENTS

-

DATAPATH ELEMENTS

-

REGISTER FILES

-REGISTER LAYOUT

For writing to a register, we include a write address with decoder. •

A given

Write Address

(with

Write Enable = 1

) selects which register, 0

through

m

  • 1, to store the input from Data In.

Register 0Register 1

Register

m

Data

Out

Data

In

n

n

w

0

w

1

w

m

1

Decoder

m

Write

Address

Write

Enable

r

1

r

m

1

r

0

INTRO. TO COMP. ENG.

CHAPTER XI-

REGISTER FILES

READ DECODER

DATAPATH ELEMENTS

-

DATAPATH ELEMENTS

-

REGISTER FILES

-REGISTER LAYOUT-WRITE DECODER

For reading from a register, we include a read address with decoder. •

A given

Read Address

(with

Read Enable = 1

) selects which register, 0

through

m

  • 1, to read from and output to Data Out.

Could have multiple

data outputs

with multiple

read address

decoders.

Register 0Register 1

Register

m

Data

Out

Data

In

n

n

w

0

w

1

w

m

1

r

0

r

1

r

m

1

Decoder

m

Read

Address

Read

Enable

INTRO. TO COMP. ENG.

CHAPTER XI-

ADDER/SUBTRACTOR

GENERAL UNIT DIAGRAM

DATAPATH ELEMENTS

-

REGISTER FILES

-WRITE DECODER-READ DECODER-32X32 REGISTER FILE

An

n

-bit adder/subtractor unit is often illustrated as follows.

This unit would have

n

full-adders internally.

adder/subtrator

unit

A

B

F

n

n

n

a

s

enable

Select either

addition (

or subtraction (

Enable unit (

or disable unit (

INTRO. TO COMP. ENG.

CHAPTER XI-

ADDER/SUBTRACTOR

OTHER UNIT SIGNALS

DATAPATH ELEMENTS

-

REGISTER FILES

-

ADDER/SUBTRACTOR

-GENERAL UNIT DIAGRAM

Other signals often included with an adder/subtractor are shownbelow.

A

B

F

n

n

n

a

s

enable

C

in

Carry-in

or Borrow-in

Carry-out

or Borrow-out

C

out

Flags

- Overflow- Negative (F<0?)- Zero (F=0?)

INTRO. TO COMP. ENG.

CHAPTER XI-

LOGICAL UNIT

GENERAL UNIT DIAGRAM

DATAPATH ELEMENTS

-

REGISTER FILES

-

ADDER/SUBTRACTOR

-

LOGICAL UNIT

-INTRODUCTION

Below is a general unit diagram for an

n

-bit logical unit.

Logical operations, such as

AND

OR

NOT

NAND

NOR

/etc., are done for

each bit of

and

to form

logical

unit

A

B

F

n

n

n

LF

enable

Enable unit (

or disable unit (

Logical Function (LF)

on 2 bits

A

B

F

INTRO. TO COMP. ENG.

CHAPTER XI-

LOGICAL UNIT

4-BIT LOGICAL FUNCTIONS (LF)

DATAPATH ELEMENTS

-

ADDER/SUBTRACTOR

-

LOGICAL UNIT

-INTRODUCTION-GENERAL UNIT DIAGRAM

Recall the possible logic functions for two bits,

and

We can use the column

F

n

as the 4-bit LF input for the logical unit.

A

B

A

B

F

0

F

1

F

2

F

3

F

4

F

5

F

6

F

7

F

8

F

9

F

10

F

11

F

12

F

13

F

14

F

15

AB

A

B

A

B

AB

A

B

A

B

B

A

A

B

Null

Identity

Inhibition

Implication

INTRO. TO COMP. ENG.

CHAPTER XI-

LOGICAL UNIT

BIT SLICE IMPLEMENTATION

DATAPATH ELEMENTS

-

LOGICAL UNIT

-GENERAL UNIT DIAGRAM-4-BIT LOGICAL FUNCTIONS-BIT SLICE IMPLEMENTAT.

The following are example LF inputs for a logical unit bit slice.

4X

MULTIPLEXER

S

1

S

0

F

A

B

E

Module Enable

OR

function

4X

MULTIPLEXER

S

1

S

0

F

A

B

E

Module Enable

NAND

function

AB

A

B

INTRO. TO COMP. ENG.

CHAPTER XI-

SHIFT UNIT

INTRODUCTION

DATAPATH ELEMENTS

-

LOGICAL UNIT

-GENERAL UNIT DIAGRAM-4-BIT LOGICAL FUNCTIONS-BIT SLICE IMPLEMENTAT.

We have already discussed the bulk about shift units in previouschapters.

As given in the Free-Doc, there are different types of shift units. •

Logical shift

Arithmetic shift

Circular shift (this is just a rotate unit)

We want to discuss an implementation, the barrel shifter, that will beuseful in our single cycle datapath computer we will design nextchapter.

INTRO. TO COMP. ENG.

CHAPTER XI-

SHIFT UNIT

P

-SHIFTER BIT SLICE

DATAPATH ELEMENTS

-

LOGICAL UNIT

-

SHIFT UNIT

-INTRODUCTION-GENERAL UNIT DIAGRAM

Previously, we discussed the

p

-shifter but not its implementation.

A

p

-shifter shifts the value to the left or right by

p

-bits.

A bit slice view of a

p

-shifter for

n

th bit could be as follows.

Notice that this can

ONLY

shift by

p

-bits. It is

hardwired

to shift

p

-bits.

4X

MULTIPLEXER

S

1

S

0

F

s

d

A

n

p

E

Module Enable

A

n

p

A

n

s

0 = no shift1 = shift

d

0 = left1 = right

INTRO. TO COMP. ENG.

CHAPTER XI-

SHIFT UNIT

K

-SHIFTER BIT SLICE

DATAPATH ELEMENTS

-

SHIFT UNIT

-INTRODUCTION-GENERAL UNIT DIAGRAM-

P

-SHIFTER BIT SLICE

A useful type of

p

-shifter is when p = 2

k

for some positive integer

k

A 2

k

-shifter allows use to build a barrel shifter.

4X

MULTIPLEXER

S

1

S

0

F

s

d

A

n

k

E

Module Enable

A

n

k

A

n

s

0 = no shift1 = shift

d

0 = left1 = right

INTRO. TO COMP. ENG.

CHAPTER XI-

SHIFT UNIT

SAMPLE BARREL SHIFTER

DATAPATH ELEMENTS

-

SHIFT UNIT

P

-SHIFTER BIT SLICE

K

-SHIFTER BIT SLICE

-BARREL SHIFTER

We will do some exampleswith the following arbitrary n

-shifter on a 16-bit input.

Note that this barrel shiftercan shift the input by 15 bitsin either direction.

-shifter

-shifter

-shifter

F

A

s

d

s

s

-shifter

s

INTRO. TO COMP. ENG.

CHAPTER XI-

SHIFT UNIT

BARREL SHIFTER: EXAMPLE

DATAPATH ELEMENTS

-

SHIFT UNIT

K

-SHIFTER BIT SLICE

-BARREL SHIFTER-SAMPLE BARREL SHIFTER

For example, consider theinput of

If we want to shift this value to the

left

by

, we need

the input

d = 0 s = (s

3

s

2

s

1

s

0

Note: This example is for a logical shift.

-shifter

-shifter

-shifter

s

d=

s

s

-shifter

s