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Main points of this exam paper are: Decimal Significant, Maximum Credit, Decimal Notation, Hexadecimal Notation, Expressed in Decimal, Sequential Values, Bit Representations, Transparent Latch, Draw Crosshatch, Transparent Latches
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4 problems, 5 pages Exam Two 27 October 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 total 40 18 30 12 100
4 problems, 5 pages Exam Two 27 October 2010 Problem 1 (4 parts, 40 points) Safety in Numbers Part A (10 points) Convert the following notations: binary notation decimal notation 1 0111 1100.
binary notation hexadecimal notation 101 1001 0101.0101 101 8B6.3C Part B (12 points) For the 28 bit representations below, determine the most positive value and the step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. Signed representations are two’s complement. representation most positive value step size unsigned fixed-point (26 bits). (2 bits) signed integer (28 bits). (0 bits) signed fixed-point (21 bits). (7 bits) signed fixed-point (14 bits). (14 bits) Part C (6 points) A 40 bit floating point representation has a 30 bit mantissa field, a 9 bit exponent field, and one sign bit.
Part D (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a five bit unsigned fixed-point and five bit two’s complement fixed-point representations.
result unsigned error? □ no □ yes □ no □ yes □ no □ yes □ no □ yes signed error? □ no □ yes □ no □ yes □ no □ yes □ no □ yes
4 problems, 5 pages Exam Two 27 October 2010 Problem 3 (3 parts, 30 points) Accountable Part A (10 points) Design a toggle cell using transparent latches , 2to1 muxes , and inverters (use icons, labeling inputs & outputs ). Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR , clock inputs Φ 1 and Φ 2 , and an output Out. The CLR signal has precedence over TE. Also complete the behavior table for the toggle cell. TE Out CLR (^) Φ (^1) Φ 2 TE CLR CLK Out 0 0 ↑↓ 1 0 ↑↓ 0 1 ↑↓ 1 1 ↑↓ Part B (10 points) Now combine these toggle cells to build a divide by 6 counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems.
Out TE CLR Out TE CLR Out
4 problems, 5 pages Exam Two 27 October 2010 Part C (10 points) Build a stopwatch that counts seconds and minutes using divide by N counters drawn below. Be sure to fill in the needed divider for seconds, tens of seconds, and minutes. Use any basic gates you require. Assume a one hertz clock is already connected. Problem 4 (1 parts, 12 points) Minimal Packaging Implement a 4to1 multiplexer using only pass gates and inverters. Label all inputs and outputs.
Out Max Count Divide by __ CE Out Max Count Divide by __ CLR Out Max Count Divide by __ CLR (^) CE
