Download SRGA-UT Design: A Self-Reconfigurable Gate Array with 8x8 Array Implementation and more Papers Digital Systems Design in PDF only on Docsity!
To the Graduate Council:
I am submitting herewith a thesis written by Gabriel Cozmin Chereches entitled
“Design and Verification of a Reusable Self-Reconfigurable Gate Array
Architecture”. I have examined the final electronic copy of this thesis for form
and content and recommend that it be accepted in partial fulfillment of the requirement for the degree of Master of Science, with a major in Electrical Engineering.
Dr. Don Bouldin Major Professor
We have read this thesis and recommend its acceptance:
Dr. Gregory Peterson
Dr. Itamar Elhanany
Accepted for the Council:
Anne Mayhew Vice Chancellor and Dean of Graduate Studies
(Original signatures are on file with official student records.)
Design and Verification o a Reusable Self-Reconfigurable
Gate Array Architecture
f
A Thesis
Presented for the
Master of Science Degree
University of Tennessee, Knoxville
Gabriel Cozmin Chereches
December 2005
Abstract
This thesis presents the design and verification of a Self-Reconfigurable Gate
Array architecture (SRGA-UT) created for reuse, and available with a step-by-
step tutorial and comprehensive documentation.
The original SRGA [1], created at the University of Southern California, is an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to a unified on-chip configuration/data memory. The key architecture that enables the above two features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at the parent nodes.
The SRGA-UT was adapted by making necessary modifications to the original
design, to be implemented using the available University of Tennessee electronic design automation tools. An 8x8 array of PEs (Processing Elements) was synthesized and routed targeting a standard cell library for a 0.18 μm process. The synthesized design can store eight configuration contexts in each PE (this number can be modified by editing the Verilog files). The place and route generated a core-chip size of 5,413,300 μm^2 , and contains 354,053 number of
gates. The step-by-step tutorial demonstrates that the SRGA-UT design is
capable to switch context and perform memory access operations in a single clock cycle.
ModelSim tools were used for verification and simulation at all levels, Design Compiler executed the synthesis and created the netlist design, and First Encounter SoC performed the place and route and created the delay constraints.
iii
Table of Contents
- Chapter 1 Introduction
- 1.1 Thesis Goals
- 1.2 Outline of Thesis
- Chapter 2 Background
- 2.1 Reconfigurable Technology
- 2.2 Design Reuse
- 2.3 SRGA-USC
- Chapter 3 Component Background
- 3.1 Components Overview
- 3.2 Registers
- 3.3 Configuration Word
- 3.4 Logic Cell
- 3.5 Memory Cell
- 3.6 Switch Structure
- 3.7 PE Structure
- 3.8 2x2 Array
- 3.9 8x8 Array
- Chapter 4 SRGA-UT Implementation
- 4.1 SRGA-UT Overview
- 4.2 EDA Tools
- 4.3 Setting up Files
- 4.4 8x8 Array Step-by-Step Tutorial
- Array 8x8 Pre-Synthesis
- Array 8x8 Synthesis
- First Encounter Tools
- Step 1: Setting up the files
- Step 2: Import the Design
- Step 3: Specify the Chip Size
- Step 4: Power Planning
- Step 5: Global Net Connections
- Step 6: Standard Cell Placement
- Step 7: Add Filler Cells
- Step 8: Route Power
- Step 9: Final Route
- Step 10: Extract RC
- Step 11: Calculate Delay
- Step 12: Results, Save, and Restore Design
- Final Layouts
- Array 8x8 Post Layout Simulation
- Chapter 5 Implementing theSRGA-UT Sub-Designs
- 5.1 Logic Cell Implementation
- Logic Cell Pre-Synthesis
- Logic Cell Synthesis
- Logic Cell Place and Route
- 5.2 Memory Cell Implementation
- 5.3 Switch Implementation
- 5.4 PE Implementation
- 5.5 2x2 Array Implementation - Possibilities Chapter 6 SRGA-UT Results, Conclusion and Future
- 6.1 Results
- 6.2 Conclusion and Future Possibilities
- Reference
- VITA
- Figure 2.2.1: Design for Reuse Diagram [5] List of Figures
- Figure 2.3.1: SRGA Architecture
- Figure 3.2.1: OR and MOR Registers
- Figure 3.2.2: Periphery Registers (a) N x N Array of PEs [1] (b) PE
- Configuration File........................................................................................ Figure 3.3.1: Configuration Word Format (a) Diagram and (b) From
- Figure 3.3.2: Full Add Configuration (a) Truth Table (b) LUT
- Figure 3.3.3: Full Subtract Configuration (a) Truth Table (b) LUT...................
- Figure 3.4.1: (a) LUT Structure and (b) Flip-Flop Structure...........................
- Figure 3.4.2: Logic cell Structure [1]............................................................
- Figure 3.4.3: Internal Functions of the LUT
- Figure 3.4.4: Input and Output Set of Wires for the Logic Cell Muxes
- Figure 3.5.1: Memory Block Structure [1].....................................................
- Figure 3.5.2: Defining the Size of the Memory Array
- Figure 3.6.1: Switch Structure.....................................................................
- Figure 3.7.1: PE Structure [1]
- Figure 3.8.1: Structure of the 2x2 Array.......................................................
- Figure 3.9.1: Structure of the 8x8 Array.......................................................
- Figure 4.2.1: SRGA-UT Design Flow.............................................................
- Figure 4.4.1: Configuration Word Format for the 8x8 Array
- Figure 4.4.2: Importing Configuration Word Section oftest_array8x8.v
- Figure 4.4.3: Assigning Inputs to the 8x8 Array
- Figure 4.4.4: Array 8x8 Pre-Synthesis - Loading Memory Blocks.....................
- Figure 4.4.5: Array 8x8 Full Add Demo Schematic.........................................
- Figure 4.4.6: Array 8x8 Pre-Synthesis - Applications
- Figure 4.4.7: Array 8x8 Pre Synthesis Workspace
- Figure 4.4.8: Array 8x8 Synthesis - Loading Memory Blocks...........................
- Figure 4.4.9: Array 8x8 Pre-Synthesis - Applications
- Figure 4.4.11: Encounter Tools - Importing Design
- Figure 4.4.12: Encounter Tools - Specify Chip Size........................................
- Figure 4.4.13: Encounter Tools - Power Planning..........................................
- Figure 4.4.14: Encounter Tools - Global Net Connections
- Figure 4.4.15: Encounter Tools - Standard Cell Placement
- Figure 4.4.16: Encounter Tools - Cell Placement Views..................................
- Figure 4.4.17: Encounter Tools - Add Filler Cells
- Figure 4.4.18: Encounter Tools - Route Power..............................................
- Figure 4.4.19: Encounter Tools - Final Route................................................
- Figure 4.4.20: Encounter Tools - (1) Extract RC and (2) Calculate Delay.........
- Figure 4.4.21: Encounter Tools - Final Pace and Route of 8x8 Array
- Figure 4.4.22: Array 8x8 Post Layout - Loading Memory Blocks......................
- Figure 4.4.23: Array 8x8 Post Layout – Applications......................................
- Figure 5.1.1: Section of Test-bench for Logic Cell Block.................................
- Figure 5.1.2: Logic Cell - Pre-Synthesis Simulation........................................
- Figure 5.1.3: Logic Cell - Post-Synthesis Simulation
- Figure 5.1.4: Logic Cell Layout after WRoute................................................
- Figure 5.1.5: Logic Cell - Post-Layout Simulation
- Figure 5.2.1: Section of Test Bench for Memory Cell Block
- Figure 5.2.2: Memory Cell Testing
- Figure 5.3.1: Section of Test Bench for Switch Module
- Figure 5.3.2: Switch Testing
- Figure 5.4.1: PE Testing – Loading Configuration..........................................
- Figure 5.4.2: PE Testing – Operations..........................................................
- Figure 5.5.1: 2x2 Array Testing – Loading Configuration
- Figure 5.5.2: 2x2 Array Testing – Operations
- Figure 6.1.1: 8x8 SRGA-UT Results..............................................................
SoC – System on Chip SRGA – Self-Reconfigurable Gate Array
SRGA-USC – Self-Reconfigurable Gate Array - University of Southern California
SRGA-UT – Self-Reconfigurable Gate Array - University of Tennessee
SRR – Source Row Register
ix
Chapter 1: Introduction
1.1 Thesis Goals
The objective of this thesis was to use the open code of the Self- Reconfigurable Gate Array (SRGA) architecture, created by the Department of EE-Systems at University of Southern California and the Department of Mathematics at the University of Trento (Italy), and make the minimum adjustments necessary to adapt and implement using the available EDA (electronic design automation) tools at the Department of ECE at the University
of Tennessee. The outcome of this thesis was to end up with aSRGA-UT design
for reuse, accessible with a step-by-step tutorial and comprehensive documentation.
To achieve this goal, a great deal of knowledge of theSRGA-USC architecture
was required. The first step was to examine the RTL (register transfer level) design, make the appropriate adjustments and pass the pre-synthesis verification stage. The second challenge was to synthesize the RTL design, create the netlist and pass the synthesis verification stage. And the last step was to generate the place and route from the netlist design, produce the timing delay files, and test the final design for proper functionality.
The EDA tools used to implement the SRGA were: ModelSim for verification and simulation at all stages, Design Compiler for synthesis and creating the netlist, and First Encounter for performing the place and route and creating the delay files.
The fifth chapter shows the implementation of the 8x8 array sub-blocks in the same manner as the tutorial. Some blocks were small enough to be proven just by verifying the pre-synthesis RTL step.
The sixth chapter will describe the results of the SRGA-UT implementation and
followed by the conclusion remarks and suggestions for future possibilities. The overall thesis provides a detailed documentation for a reusable design.
Chapter 2: Background
2.1 Reconfigurable Technology
Reconfigurability denotes the potential of a system to dynamically change its behavior usually in response to changes in its environment. In the computing world, the Field Programmable Gate Arrays (FPGAs) are the most popular means of accomplishing reconfigurability. An FPGA consists of an array of programmable logic elements and programmable interconnects. The logic elements can be logic gates (AND, OR, XOR, Invert), lookup tables (memory usually RAM), or flip-flops [2]. The interconnects allow the logic elements to be connected as needed by the design.
The logic elements and interconnects can be programmed by the customer so that the FPGA can perform a certain functionality. This functionality can be reconfigured to suit new application requirements desired by the customer by writing appropriate bits into the configuration memory. The challenges with most FPGAs however, whether they are reconfigured at compile time or runtime, is that they require an external source to execute the reconfiguration.
A device, that is capable to generate configuration bits at runtime and use them to modify its own configuration, exhibits self-reconfiguration. A self- reconfigurable device needs to be able to store multiple contexts of configuration information and context switch between them. The configured logic should be able to access any of the contexts of information stored and perform self- reconfiguration by modifying the contents of the information stored. When the configured logic has made the modifications to the configuration information, the device should be able to switch context to any of the contexts of configuration stored. For an efficient self-reconfiguration to occur, the device should be able 4
Figure 2.2.1: Design for Reuse Diagram [5]
number of sub-designs, given that each module has the same complexity. During development with planned design reuse, the designer will spend more time in creating a reusable block by providing comprehensive documentation and more adaptable interface.
The design for reuse techniques are closely studied in today’s SoC development. A basic combination of such reusable features is known as a platform. The platform used to implement a SoC greatly impacts all of the issues and is the fundamental decision the hardware designers must make at the start of each new project. By 2010 the percentage of IP contained in a System-on-Chip application is predicted to grow to 95% [6].
One of the goals for this thesis is to end up with a SRGA UT design for reuse,
accessible with a step-by-step tutorial and comprehensive documentation.
2.3 SRGA-USC
The original Self-Reconfigurable Gate Array Architecture [1] is an open core design implemented by the Department of EE-Systems at University of Southern California and the Department of Mathematics at the University of Trento (Italy).
6
The reconfigurable device allows single cycle context switching and single cycle random access to the unified on-chip memory which stores the configuration data. Both features are necessary for efficient self-reconfiguration. The context switching feature permits arbitrary regions of the chip to selectively switch context. The memory access feature allows data transfer between logic cells and memory locations as well as between memory locations. A mesh of trees based interconnects with logic cells and memory blocks at the leaf nodes and identical switches at the other nodes make it possible to perform the above features. Figure 2.3.1 shows the basic SRGA architecture of a 4x4 array of PEs.
The architecture can be of any N x N array of PEs. The PE sits at the leaf node of the mesh of trees interconnects and is composed of a logic cell, memory block, and memory interface. Each switch is identical except that some switches are connected in a column mesh network and some are connected in a row mesh network. Each PE is connected to a row switch and a column switch.
Figure 2.3.1: SRGA Architecture 7
The memory interface generates the proper inputs to the memory block and to some extent to the logic cell by taking the register signals and combining them through basic logic gates to create the appropriate signals.
Chapter 3: Component Background
3.1 Components Overview
This chapter will describe in details the structure of each component of the
SRGA-UT, which includes the changes made to the original SRGA-USC design.
The changes, which will be pointed out throughout the next three chapters, were necessary for the design to be adapted and able to implement using the
available EDA tools. TheSRGA-UT design retains the overall original architecture
but was mostly adjusted to be able to pass the verification stages of pre- synthesis, synthesis and place and route.
TheSRGA-UT architecture consists of an array of N x N array of PEs. The PE sits
at the leaf node of the mesh of trees interconnects and is composed of a logic cell, memory block, and memory interface (described later in this chapter). Each switch is identical except that some switches are connected in a column mesh network and some are connected in a row mesh network. Each PE is connected to a row switch and a column switch.
The N x N array of PEs is configured by inputting configuration contexts (described in section 3.3) into the memory array of each PE – which can store
eight contexts of configuration. Once the memory is loaded, theSRGA-UT can
switch context and perform memory operations in a single clock cycle. This is done through a number of global and periphery registers.
3.2 Registers
TheSRGA-USC contains three global registers and four periphery registers.
The memory, interface, module takes signals from the registers and creates the
10
