ECE3050 Summer 2005
Design Project
The figure shows the circuit diagram of an operational amplifier. The object of this assignment is to
calculate the circuit elements and perform a SPICE simulation. You must write the netlist or SPICE
deck for the assignment. You are not permitted to use a schematic editor to generate the netlist.
To do this, you use an ascii text editor. Such an editor is part of both PSpice, Notepad, or Wordpad
.Thefirst line of the netlist must be a title line. You can title it ECE 3050 DESIGN PROJECT.
A suggested name for the ascii netlist file is opamp.cir. Comment lines must be preceded by an
asterisk. Continuation lines must be preceded by a plus sign followed by a space. Write the netlist
using all capital letters.
For the JFET and BJTs in the circuit, you are to use the following SPICE MODEL statements:
J1.MODEL MNJF1 NJF BETA=5E-4 VTO=-3 LAMBDA=0.0125
Q1,Q2,Q5−Q7.MODEL MNPN1 NPN IS=1.26E-14 BF=149 VA=150
Q3,Q4,Q8.MODEL MPNP1 PNP IS=1.26E-14 BF=149 VA=150
where BF for the BJT is its β. The other parameters should be self explanatory. In your calculations
for the resistors, you can neglect the Early effect, i.e. set VA=∞and λ=0. In addition, with the
exception of Q5and Q6, neglect all BJT base currents, i.e. set IB=0.
First, label the node numbers for each node in the circuit. The ground node must be labeled 0.
Voltage sources are of the form VX N1 N2 AC ACVAL DC DCVAL,whereVX isthesourcename,N1
is the positive node, N2 is the negative node, ACVAL is the ac phasor value, and DCVA is the dc
value. Current sources are of the form IX N1 N2 AC ACVAL DC DCVAL. The arrow in the current
source symbol points from the N1 node to the N2 node. Resistors and capacitors are specified as
RX N1 N2 VALUE and CX N1 N2 VALUE. BJTs are specified as QX NC NB NE QMDL,whereQX is the
BJT name, NC,NB,andNE, respectively, are the collector, base, and emitter nodes, and QMDL is the
model name. JFETs are specified as JX ND NG NS JMDL,whereJX is the JFET name, ND,NG,and
NS, respectively, are the drain, gate, and source nodes, and JMDL is the model name.
The first step in any design is to specify the dc bias values. These are specified to be V+=18V,
V−=−18 V,VO=0V,ID1=1.5mA,IC3=0.5mA,IC4=1.5mA,IC6=2mA,andIE7=IE8=
2mA. The small-signal ac gain with feedback can be approximated by the equation
vo
vi
=1+RF2
RF1
This is the familiar gain formula for the non-inverting op-amp amplifier. The gain is specified to
have a value of 10 (20 dB). The value of RF2is to be 10 kΩ.ThevalueofCFis to be calculated
so that 1/(2πRF1CF)=10Hz.ThevalueofRLis specified to be RL=1kΩ.Thevalueof
both R1Aand R1Bare specified to be equal to RF2.ThevalueofC1is to be calculated so that
1/(2πR1BC1)=10Hz.ThevaluesofRE7and RE8are to be 10 Ω.
The circuit is to be designed for the gain-bandwidth product fx=1MHzand the slew rate SR =
10 V/µs. The approximate design equations which set these parameters are
fx=1
4π(re+RE)Cc
SR =ID1
2Cc
where re=2VT/ID1. You can use these equations to solve for the values of REand Cc. The default
value of VTin SPICE is 25.86 mV. This value should be used in the calculations.
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