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Lab 1. Introduction to Modelsim (Lab Session 1)
This tutorial^1 provides an introduction to simulation of logic circuits using the ModelSim Simulator. It shows how the simulator can be used to perform functional simulation of a circuit specified in a hardware description language. It is intended for a student in an introductory course on logic circuits, who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation.
1.1. Background:
ModelSim is a powerful simulator that can be used to simulate the behaviour and performance of logic circuits. To download ModelSim and Quartus II FPGA programming tool, use the following link: https://fpgasoftware.intel.com/13.0sp1/?edition=web This tutorial gives a rudimentary introduction to functional simulation of circuits, using the capability of ModelSim. It discusses only a small subset of ModelSim features.
The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response. The user can use the Waveform Editor to represent the input signals as waveforms.
This tutorial is aimed at the reader who wishes to simulate circuits defined by using the SystemVerilog hardware description language. Same methodology applies for the other languages as well.
1.2. Introduction
There are two important elements we should familiarise ourselves with in ModelSim. They are: Library and Project. A Library provides an environment for you to compile and simulate your design, while a project provides a place to contain all relevant files and settings for an independent design including its working library.
Library is a directory that contains compiled design units such as modules. There are two types of libraries:
- Resource Library: Contains static contents, such as the compiled version of standard modules. Resource libraries, such as ieee , can be found in the library pane on the left hand side of the ModelSim window.
- Working Library: Contains the compiled version of the design. The contents of a working library change every time you compile your design. The default working library in ModelSim is named work and is predefined in the ModelSim compiler. The working library when created or linked to your source code can be accessed through the library pane on the left-hand side of the ModelSim window.
The project is a collection of various files for designs under test, such as HDL source files, local working libraries, references to resource libraries, and simulation configuration files.
1.3. Design Project:
To illustrate the simulation process, we will use a very simple logic circuit that implements the majority function of three inputs, x1, x2 and x3. The circuit is defined by the expression: 𝑓𝑓(𝑥𝑥 1 , 𝑥𝑥 2 , 𝑥𝑥 3 ) = 𝑥𝑥 1 𝑥𝑥 2 + 𝑥𝑥 1 𝑥𝑥 3 + 𝑥𝑥 2 𝑥𝑥 3 ModelSim performs simulation in the context of projects – one project at a time. A project includes the design files that specify the circuit to be simulated. We will first create a directory (folder) to hold the project used in the tutorial. Create a new directory and call it Lab.
(^1) Adapted from “Introduction to Simulation of VHDL Designs Using ModelSim Graphical Waveform Editor”, Altera Corporation –University Program,
Open the ModelSim simulator. In the displayed window select File New Project, as shown in Figure 1.
Figure 1.1: The ModelSim Window
A Create Project pop-up box will appear, as illustrated in Figure 1.2. Specify the name of the project; we chose the name majority. Use the Browse button in the Project Location box to specify the location of the directory that you created for the project. ModelSim uses a working library to contain the information on the design in progress; in the Default Library Name field we used the name work. Click OK.
Figure 1.2 Create Project Window
Now we are going to add a SystemVerilog source file to the project. You can either use the pop-up window in Figure 1.3 or follow File New Source SystemVerilog. Click on Create New File , enter the file name as majority.sv and change file type to SystemVerilog. Click OK, then close the windows (also, using Add Existing File you could add any file you created earlier to the project).
Figure 1.3: Add Items Window
At this point, the Modelsim window will look like as shown in Figure 1.4. Observe that there is a question mark in the Status column. This is because your code has not yet been successfully compiled (and in this case, you haven’t even written down the code).
Figure 1.6 Updated ModelSim window with successfully simulated code
1.4. Creating Waveforms for Simulation:
To perform simulation of the designed circuit, it is necessary to enter the simulation mode by selecting Simulate Start Simulation and you get a window as shown in Figure 1.7.
Figure 1.7 Start Simulation Window
Expand the work directory and select the design called majority, as shown in the figure. Then click OK. Now, in the main Modelsim window, an Objects window appears. It shows the input and output signals of the designed circuit, as depicted in Figure 1.8.
Figure 1.8 ModelSim Window with Input and Output Signals
Select all the input and output signals (also you could select only the signals you may want to see) and right click. Then as shown in Figure 1.9, click on Add Wave.
Figure 1.9 Adding Waveforms to the Wave Window
All the selected waveforms will appear in the Wave tab ( see Figure 1.10).
Figure 1.10 Wave window with Signals
To simulate the circuit we must first specify the values of input signals, which can be done by several ways (you can follow Modelsim User’s Manual for this). One way is to right click on the signal in the wave window and then Force a signal. In this lab, we are going to use an efficient method using TCL based script and these commands are entered using the transcript window (See Figure 1.11).
Figure 1.11 Transcript Window
In the transcript window type in the following ModelSim commands at the prompt.
force x1 0 ↵ (Forces a logic ‘0’ to signal x1) force x2 1 ↵ force x3 0 ↵
1.5. Creating a macro .do file:
Once you have finished the simulation, create a macro file from the commands you have used and then you can run the same simulation just by calling the macro file. It is very useful, since you always modify your design and you must simulate it again with the same data as before. To create a .do file, click on File New Source Do (See Figure 1.14). Figure 1.14 Creating a .do File Enter the following commands in the blank file and save it as test_majority.do in the same project folder Lab1. To run the macro file, you can either enter the command: do test_majority.do at Modelsim Command line or just follow Tools TCL Execute Macro and select the file as shown in Figure 1.15. If you want start from the beginning, you may clear the old results using Simulate>Restart otherwise
- pattern simulation starts from where it stopped.
- force x1
- force x2
- force x3
- run
- #pattern
- force x1
- force x2
- force x3
- run
- #pattern
- force x1
- force x2
- force x3
- run
- #pattern
- force x1
- force x2
- force x3
- run
pattern
- force x1
- force x2
- force x3
- run
pattern
- force x1
- force x2
- force x3
- run
- #pattern
- force x1
- force x2
- force x3
- run
- #pattern
- force x1
- force x2
- force x3
- run
Figure 1.15: Executing a .do file
Once you run test_majority.do, your outcome should be as shown in Figure 1.16.
Figure 1.16 Simulated output for majority.vhd
Add following commands to at the very beginning of test_majority.do file and save it. This new .do file will load the design and waveforms, simulate, and display results. Compile your code, and then run the following script. You don’t have to follow Simulate Start Simulation.
load the file to simulate
vsim majority
windows for viewing
view signals view wave
add all the waveforms to viewing window
you can add them selectively too e.g. add wave x
add wave *
NEXT SECTION IS OPTIONAL (need more understanding on SystemVerilog!!!)
1.6. Advanced .do Files (optional):
Macro (do) files are files that contain ModelSim and sometimes Tcl commands to control the simulator and the simulation. Macro files are useful files that can help you to reduce repetitive work like setting up the simulator (open debug windows) or simulation (initialize signals) and so on. You can even use them run the whole
restart the simulation
restart -f
set the time units to ns
configure wave -timelineunits ns
add wave -unsigned *
list all signals in decimal format
add list -unsigned *
set errorCount 0 set step 10ns set runtime $step
for {set i 0} {$i < 16} {incr i} { force -freeze A 10#[expr $i] $runtime
set BValue [expr round(15*rand())] force -freeze B 10#[expr $BValue] $runtime
run $runtime
Calculate what we should get
set ExpectedResult [expr $i + $BValue ]
simulated result
set simulatedResult [ examine -unsigned /T ] #check for errors if { $ExpectedResult != $simulatedResult } { echo "ERROR! " #break the for loop to stop the simulator set errorCount [ expr $errorCount + 1] break
set runtime [expr $runtime + $step] } }
Concluding Remarks: The purpose of this tutorial is to provide a quick introduction to ModelSim, explaining only the rudimentary aspects of functional simulation that can be performed using the ModelSim Commands. More details about the ModelSim GUI and its use in simulation can be found in the ModelSim SE User’s Manual, which is available as part of an installed ModelSim-SE simulator (go to HelpPDF Documentation).
