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DIGITAL ELECTRONICS DOCX, Exercises of Digital Electronics

Adamas University Digital Electronics

DIGITAL ELECTRONICS QUESTION ANSWERS DOCX

Typology: Exercises

2023/2024

Uploaded on 11/13/2025

pat-ghosh 🇮🇳

1 document

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SUB -DLD CODE-MCPC1001

PART -2

2.a) In JK flip flop when both the J and K inputs are set to 1, and the clock pulse is high for a

duration longer than the propagation delay of the flip flopThis causes the output to toggle

continuously which leading to an unpredictable state - This is called race around condition.

Using Master Slave FlipFlop we can solve this problem

The Master Slave Flip-Flop consist of two gated SR latches. The first latch act as a

master latch and the second latch act as a slave latch. The output of the master

latch is connected to the slave latch. The Q’ output of the slave latch is

connected back to the master latch where S input is applied and similarly, Q

output is connected back where the R input is applied. The clock signal to the

slave latch is applied through an inverter. That means when clock signal is high

then master is enabled and slave is disabled. Similarly, when clock is low then

slave is active and master is disabled.

2.b) A full adder is a digital circuit that performs addition. Full adders

are implemented with logic gates in hardware. A full adder adds three

one-bit binary numbers, two operands and a carry bit. The adder

outputs two numbers, a sum and a carry bit.

it generates a carry out to the next addition column. Then a Carry-in

is a possible carry from a less significant digit, while a Carry-out

represents a carry to a more significant digit.

Discover Exercises of Digital Electronics Adamas University

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SUB -DLD CODE-MCPC PART - 2.a) In JK flip flop when both the J and K inputs are set to 1, and the clock pulse is high for a duration longer than the propagation delay of the flip flop This causes the output to toggle continuously which leading to an unpredictable state - This is called race around condition. Using Master Slave FlipFlop we can solve this problem The Master Slave Flip-Flop consist of two gated SR latches. The first latch act as a master latch and the second latch act as a slave latch. The output of the master latch is connected to the slave latch. The Q’ output of the slave latch is connected back to the master latch where S input is applied and similarly, Q output is connected back where the R input is applied. The clock signal to the slave latch is applied through an inverter. That means when clock signal is high then master is enabled and slave is disabled. Similarly, when clock is low then slave is active and master is disabled. 2.b) A full adder is a digital circuit that performs addition. Full adders are implemented with logic gates in hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit. The adder outputs two numbers, a sum and a carry bit. it generates a carry out to the next addition column. Then a Carry-in is a possible carry from a less significant digit, while a Carry-out represents a carry to a more significant digit.

d).JK Flip-Flip is basically a gated SR flip-flop which has an additional input that is clock input. It prevents the invalid output that may be obtained when both the inputs are 1. Whereas D Flip-Flop is a modified SR flip-flop which has an additional inverter. It prevents the inputs from becoming the same value.

Step-1: We construct the characteristic table of D flip-flop and

excitation table of JK flip-flop.

2. f). A Synchronous Counter is a type of counter where all the flip-flops

are controlled by a single common clock signal. This ensures that all flip-

flops in the counter change their states simultaneously, leading to

synchronized counting. These are the counters in which we use a

universal clock that is common to all flip-flops.

Design for Mod-N counter :

The steps for the design are –

Step 1 : Decision for number of flip-flops –

Example : If we are designing mod N counter and n number of flip-flops

are required then n can be found out by this equation.

N <= 2n

Here we are designing Mod- 4 counter Therefore, N= 4 and number of

Flip flops(n) required is

For n =1, 4<=2, which is false.

Fo Therefore number of FF required is 4 for Mod-10 counter.

There fore number of FF required is 2 for Mod-4 counter.

2.h) VHDL Code for 1 bit half adder:

Library ieee;

use ieee.std_logic_1164.all;

entity half_adder is

port(a,b:in bit; sum,carry:out bit);

end half_adder;

architecture data of half_adder is

begin

sum<= a xor b;

carry <= a and b;

end data;

2.i) VHDL Code for 8x1MUX:

1. PR = 0 , Q = 1

2. CLR = 0 , Q = 0

These two values(always fixed) are independent with the input D and the Clock pulse (CLK). Working The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed to the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3. The pre-set input set to 0 for the first flip flop. So, the output of the first flip flop is one, and the outputs of the remaining flip flops are 0. The output of the first flip flop is used to form the ring in the ring counter and referred to as Pre-set 1. In the above table, the highlighted 1's are pre-set 1. The Pre-set 1 is generated when o ORI input set to low, and that time the Clk doesn't care. o o When the ORI input set to high, and the low clock pulse signal is passed as the negative clock edge triggered. A ring forms when the pre-set 1 is shifted to the next flip-flop at each clock pulse.